Afraid of mesh-based clock topologies? You should be

Afraid of mesh-based clock topologies? You should be
by Daniel Payne on 03-18-2024 at 10:00 am

mesh-based clock topology

Digital logic chips synchronize all logic operations by using a clock signal connected to flip-flops or latches, and the clock is distributed across the entire chip. The ultimate goal is to have a clock signal that arrives at the exact same moment in time at all clocked elements. If the clock arrives too early or too late from the PLL… Read More


Feeding the Growing Hunger for Bandwidth with High-Speed Ethernet

Feeding the Growing Hunger for Bandwidth with High-Speed Ethernet
by Madhumita Sanyal on 04-10-2023 at 6:00 am

Picture2

The increasing demands for massive amounts of data are driving high-performance computing (HPC) to advance the pace in the High-speed Ethernet world. This in turn, is increasing the levels of complexity when designing networking SoCs like switches, retimers, and pluggable modules. This growth is accelerating the need for … Read More


Package Pin-less PLLs Benefit Overall Chip PPA

Package Pin-less PLLs Benefit Overall Chip PPA
by Tom Simon on 08-19-2021 at 6:00 am

Pin less PLLs from Analog Bits

SOCs designed on advanced FinFET nodes like 7, 5 and 3nm call for silicon-validated physical analog IP for many critical functions. Analog blocks have always been node and process specific and their development has always been a challenge for SOC teams. Fortunately, there are well established and endorsed analog IP companies… Read More


A Review of Clock Generation and Distribution for Off-Chip Interfacing

A Review of Clock Generation and Distribution for Off-Chip Interfacing
by Tom Dillinger on 03-09-2021 at 6:00 am

clocking

At the recent ISSCC conference, Mozhgan Mansuri from Intel gave an enlightening (extended) short course presentation on all thing related to clocking, for both wireline and wireless interface design. [1]  The presentation was extremely thorough, ranging from a review of basic clocking principles to unique circuit design … Read More


Creating Analog PLL IP for TSMC 5nm and 3nm

Creating Analog PLL IP for TSMC 5nm and 3nm
by Tom Simon on 09-01-2020 at 6:00 am

PLL Optimizations

TSMC’s Open Innovation Platform’s main objective is to create and promote partnership for producing chips. This year’s OIP event included a presentation on the joint efforts of Silicon Creations, Mentor, a Siemens business and TSMC to produce essential PLL IP for 5nm and 3nm designs. The relentless push for smaller geometries… Read More


Keeping Pace With 5nm Heartbeat

Keeping Pace With 5nm Heartbeat
by Alex Tan on 07-23-2018 at 12:00 pm

A Phase-Locked Loop (PLL) gives design a heartbeat. Despite its minute footprint, it has many purposes such as being part of the clock generation circuits, on-chip digital temperature sensor, process control monitoring in the scribe-line or as baseline circuitry to facilitate an effective measurement of the design’s power… Read More


TSMC Teamwork Translates to Technical Triumph

TSMC Teamwork Translates to Technical Triumph
by Tom Simon on 10-02-2017 at 12:00 pm

Most people think that designing successful high speed analog circuits requires a mixture of magic, skill and lots of hard work. While this might be true, in reality it also requires a large dose of collaboration among each of the members of the design, tool and fabrication panoply. This point was recently made abundantly clear … Read More


Understanding Sources of Clock Jitter Critical for SOC’s

Understanding Sources of Clock Jitter Critical for SOC’s
by Tom Simon on 05-29-2017 at 12:00 pm

Jitter issues in SOC’s reside at the crossroads of analog and digital design. Digital designers would prefer to live in a world of clocks that are free from jitter effects. At the same time, analog designers can build PLL’s that are precise and finely tuned. However, when a perfectly working PLL is inserted into an SOC, things can … Read More


Who knew designing PLL’s was so complicated?

Who knew designing PLL’s was so complicated?
by Tom Simon on 03-27-2017 at 12:00 pm

Well it comes as no surprise to those that use and design them, that PLL’s are a world unto themselves and very complicated indeed. With PLL’s we are talking about analog designs that rely on ring oscillators or LC tanks. They are needed on legacy nodes, like the ones that IoT chips are based on, and they are crucial for high speed advanced… Read More


CEO Interview: Randy Caplan of Silicon Creations

CEO Interview: Randy Caplan of Silicon Creations
by Daniel Nenni on 12-05-2016 at 7:00 am

For the next installment in our series of semiconductor CEO interviews we meet with Randy Caplan from Silicon Creations. Randy has helped build the company from a small startup to one of the world’s leading providers of interface and clocking IP. Almost every new chip developed these days has a requirement for PLLs and SerDes. Since… Read More