Jitter issues in SOC’s reside at the crossroads of analog and digital design. Digital designers would prefer to live in a world of clocks that are free from jitter effects. At the same time, analog designers can build PLL’s that are precise and finely tuned. However, when a perfectly working PLL is inserted into an SOC, things can get complicated.
On the digital side deterministic jitter can cause havoc with timing. Deterministic jitter comes from things like supply noise, duty cycle distortion, and other factors. The other variety of jitter is called random jitter, and mostly comes from variations in the VCO or PLL over a number of cycles. Random jitter is often hard to measure because it can be buried in the much higher amplitude deterministic jitter.
In a presentation prepared by Silicon Creations, they posit that deterministic jitter (the kind that can seriously affect SOC timing) is often largely a result of supply noise. The title of their presentation is “Supply Noise Induced Jitter – Don’t Let it Kill Your Chip”. They have seen deterministic jitter of up to 450ps. It’s worth noting that analog interface IP is also affected by jitter, potentially leading to higher BER and poor SNR.
Looking in more detail at the digital side, we already know that gate delay depends on voltage and temperature. Supply voltage variations caused by noise alter gate delay, which will affect clocks as well as control logic and data paths. Nice gradual shifts in supply voltage are not nearly as bad as abrupt changes while a clock edge is in flight. The results can take an extremely clean clock signal and turn it into one with detrimental levels of jitter. Additionally, longer paths are more susceptible to jitter effects.
Silicon Creations has a useful formula shown above for estimating period jitter. You can see it depends heavily on the peak to peak changes in the difference between Vdd and Vss, as well as the difference between Vdd and Vt. Silicon Creations is fine admitting that this is an approximation, not a rigorous equation. Though to make this formula useful there needs to be a way to estimate changes in Vdd. Their presentation goes into detail on methods to go through this process.
Alternatively, in many cases it can prove useful to assemble a flow for modeling jitter, rather than relying on a rule of thumb such as the one shown above. Silicon Creations customers’ have also done this with a flow based on Voltus & Tempus from Cadence. It is necessary to look at activity information and use this to derive per instance dynamic voltage drop information. Of course thermal information is needed too.
Silicon Creations closes their presentation with suggestions on how to fix chips that are broken due to jitter related issues. Their interest in this topic comes from wanting to ensure design success for customers of their PLL IP. They have had extensive experience working with SOC design teams to find solutions to chip level timing and jitter issues. Clearly this is a case of having to bring together expertise in the digital and analog domains to craft the best technical resolution.
If you want to look over the entire presentation, you can find it on their website.
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