Understanding Sources of Clock Jitter Critical for SOC’s

Understanding Sources of Clock Jitter Critical for SOC’s
by Tom Simon on 05-29-2017 at 12:00 pm

Jitter issues in SOC’s reside at the crossroads of analog and digital design. Digital designers would prefer to live in a world of clocks that are free from jitter effects. At the same time, analog designers can build PLL’s that are precise and finely tuned. However, when a perfectly working PLL is inserted into an SOC, things can … Read More