It is clear that IP companies play an important role in modern semiconductor design, in fact, I would say that they are imperative. Founded in 2006, Silicon Creations is one of those imperative IP companies that provide silicon proven IP to customers big and small around the world. To follow-up on our conversation with Silicon Creations CEO Randy Caplan, CTO Jeff Galloway provided a closer look at the technology behind their success.
What sets Silicon Creations apart technically?
First of all, I believe we’ve architected robust and versatile products. For example, we have a PLL architecture that has scaled from 65nm at company creation in 2006, down to 7nm. Over the last 10 years, it’s been ported all the way back to 180nm. The same robust proven architecture is silicon-proven from 180nm to 10nm and 7nm silicon is due very soon.
The architecture has scaled not only across geometries but also along a huge power/performance curve. For example, the same PLL architecture that allows our high speed SerDes to achieve a fantastic power/performance ratio with jitter < 400fs also allows us to be the differentiated PLL provider for 10uW PLLs for application processors and other IoT devices.
Secondly, given a robust architecture, it’s important to have a methodology to port the design from node to node. Typically, an SoC company concentrates product line on a specific geometry. An IP company like us, on the other hand, must have it’s IP available in a wide variety of nodes, or able to do so. We have a robust design flow methodology in place that allows us to port from foundry to foundry and node to node quickly and efficiently.
We have delivered approximately 300 IP products (from 7nm to 180nm), so we certainly have a very wide range of IP. We have a schematic flow, which allows our core IP to be shared across geometry and foundry, reducing time to market and reducing risk. We also have a layout flow that allows similar flexibility, further reducing risk and providing robust products across variety of nodes.
Thirdly, we have an automated test lab. We’ve characterized nearly 50 chips at this point (many in the last 5 years) and have generated over 100 test chip reports. This critical ability has allowed us to launch our customers’ 10nm products (and soon 7nm) and multi-protocol SerDes.
Figure 1 – Test lab in top gear – 100 test chip reports and counting!
Can you tell us a little more about your IoT PLL product and what makes it different, more appealing to design engineers?
Low-power and fast lock times are critical metrics for IoT PLL products. Most “low-power” PLLs are on the order of 1mW. The active power is critical for our customers, especially in leading mobile products. Our architecture achieves less than 10uW while keeping area low. Secondly, we have an innovative architecture that frequency locks in fewer than 20 cycles, or just 3 cycles if calibrated. The PLL also phase locks in fewer than 40 cycles. This capability gives us an advantage in addressing the fast lock time requirements that is critically important for IoT where the reference clock is often 32.768KHz and energy shouldn’t be lost waiting on lock.
You mention the PLL architecture that is in your 10uW IoT PLL is also in your Multi-Protocol SerDes?
Yes, the same low power architecture is used. But we size the multi-protocol SerDes PLL on a different point on the power/jitter tradeoff curve, obviously . Nevertheless, we still achieve excellent power efficiency. For example, we have a 28nm product with ~5mW/Gb/s for SerDes operation that achieves < 400fs RMS RJ for 10G-KR. The low jitter for TX and RX along with an optimized front-end equalizer (CTLE+DFE) allows the SerDes to communicate over very long backplanes and other difficult channels.
Figure 2: SerDes Eye at 12.5Gb/s
We think this SerDes product has the most flexibility on the market. Our lead customer for this was an FPGA customer (MicroSemi), so needed the flexibility and functionality. This single PMA can cover a 50:1 range from 250Mb/s to 12.7Gbs, and cover the following standards:
Table 1 – Multi-Protocol Standards
Your products look differentiated, but have they found commercial success?
We have a large number of production chips in silicon from 7nm (this month) to 180nm.
Figure 3 – Cumulative Chips in Production w/ Silicon Creations IP
Is the broad adoption because of performance?
I believe a lot of the early design wins we had were based on performance. For instance, w e have a fractional-N product with long-term jitter low enough to clock AFEs or SerDes. That helps us stand out. But the same PLL, programmed to a different power/performance point, could clock digital logic power efficiently.
Figure 4 – PLL Use Case – Flexibility with Programmability
Our customers quickly realized that they could replace many different PLLs with one Silicon Creations PLL.
Due to the fractional-N capability, the PLL also can perform many frequency and phase functions such as spread-spectrum generation, DPLL/clock recovery and arbitrary phase shifting.
We put tremendous effort to focus on customer needs, and we think that it greatly differentiates us. This is one of the prominent reasons why our customers keep returning for our PLLs for their next product.
About Silicon Creations
Silicon Creations is focused on providing world-class silicon intellectual property (IP) for precision and general-purpose timing (PLLs), Chip-chip SerDes and high-speed differential I/Os. Silicon Creations’ IP is proven from 7 to 180-nanometer process technologies. With a complete commitment to customer success, its IP has an excellent record of first silicon to mass production in customer designs. Silicon Creations, founded in 2006, is self-funded and growing. The company has development centers in Atlanta, Ga., and Krakow, Poland, and worldwide sales representation. For more information, visit www.siliconcr.com.