A directed approach to reduce Risk and improve Quality
Safety and reliability are critical for most applications of integrated circuits (ICs) today. Even more so when they serve markets like ADAS, autonomous driving, healthcare and aeronautics where they are paramount. Safety and reliability transcend all levels of an integrated circuit and the quality of timing definition at every level plays a critical role in ensuring them. Every integrated circuit, small or big, uses from tens of IP’s to hundreds of them. Proper timing behavior of every component is key to the overall safety and reliability of the IC and the system the IC goes into. Creating a comprehensive set of timing arcs for the IPs is an essential component of its quality metric and ensures better safety and reliability in the end applications of the IP. It also plays a key role in the reduction of a variety of risk factors for the IP and the IC it goes into.
Timing arc generation for digital IPs is well understood and is automated. The same is not true for the analog and AMS IP’s. Timing arc generation for analog and AMS IP’s is manual. In addition, IPs get integrated into many applications beyond what an IP designer designed his/her IP for. It relies on the designer’s expertise to not miss an arc. How can you trust the SoCs that make use of such analog and AMS IP’s created using error prone methods for mission-critical applications like autonomous driving, aeronautics, healthcare? An AI-powered methodology that allows the generation of a comprehensive set of timing arcs analog/AMS IP’s – high quality and low risk – is essential for their use on mission-critical applications.
Integration of analog or AMS IP into a SoC is challenging and the larger the IP, the greater is the challenge. With analog designs being sensitive to layout, proximity and matching, the impact on timing is direct and typically ranges from delayed tape-out to silicon failure, and multiple silicon iterations.
Thanks to recent advances in artificial intelligence (AI) and machine learning (ML), automation of the timing arc generation for analog and AMS IP’s is becoming a reality. Empyrean Software, working with some key customers has taken the lead to develop the automation of timing arc creation for analog and AMS IP’s. A joint paper, Machine Learning based Timing Arc Prediction for AMS Design, with a customer (NVIDIA) was presented at the “Designer Track” of the most recent Design Automation Conference (DAC 2019) in Las Vegas, Nevada.
A webinar titled, “Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction,” will focus on the new AI-powered automated timing arc prediction and validation capability, the first commercial capability of its kind for IPs. It will talk about the motivation., technology and a methodology for using AI-powered automated timing arc prediction. The 30-minute webinar is scheduled for September 24th at 10:00 am (PST) and you can register to attend and get access to the presentation.
About Empyrean Software
Empyrean Software provides electronic design automation (EDA) software, design IPs and design services, including analog and mixed-signal IC design solutions, SoC design optimization solutions, and Flat Panel Design (FPD) solutions and customized consulting services.
Empyrean Software is the largest EDA software provider in China, and its research and development team has more than 30 years of experience in technology and product development. Our company has comprehensive cooperation with many corporations, universities and research laboratories.
Empyrean’s core values are dedication, collaboration, innovation, and professionalism. Our company is committed to working with customers and partners through win-win collaboration to achieve our common goals.