Atos Crafts NoC, Pad Ring, More Using DefactoI’ve talked before about how Defacto provides a…Read More
A Thoughtful Semiconductor Outlook – Needed Now More Than EverIf you’re not dizzy from all the changing…Read More
Collaboration Flow for Moore’s Law versus More than MooreThe current Coronavirus crisis is inflicting a lot…Read More
eFPGA - What’s Available Now, What’s Coming and What’s Possible!eFPGA is now widely available, has been used…Read More
Figure 1 Collaboration with Foundry
During the 2008 financial crisis, rumors about the end of Moore’s Law and the need for More than Moore started. I took this as an opportunity to change my focus from the traditional single-die SoC technology to multi-die ICs (2.5/3D-ICs). In these new technologies the package adds a lot of value to the complete solution. Until that time, I was used to being part of the broad and in-depth cooperation between EDA vendors and wafer foundries, developing Process Design Kits (PDKs) and Reference Design Flows. That’s the reason why I was surprised that IC assembly/test houses (a.k.a. OSATs), at that time, were not as proactive as wafer foundries. They had no design kits, nor reference flows, and the excellent engineers at the OSATs had to spend a lot of manual efforts, to meet their customers’ IC packaging and cost requirements.
Thanks to industry organizations, like the Global Semiconductor Alliance (GSA), SEMATEC, the Silicon Integration Initiative (Si2), the Electronic System Design Alliance (ESDA), MEPTEC and SEMI, who gave me “a soap-box” to better highlight the industry’s pressure for more automation between IC designers and OSATs, several OSATs have developed since, in cooperation with their EDA partners, Assembly Design Kits (ADKs) and Design Reference Flows for packages. Figure 2 shows a significantly simplified Collaboration Flow between the essential parties, to reduce package development time and engineering cost. Please, DO NOT plan on six magnitudes in package unit cost reduction. To achieve this target, IC packages would need to be shrunk so much, that nobody could see or use them anymore.
Figure 2 Collaboration with OSAT
Bottom Line: Assembly Design Kits and Design Reference Flows encourage the use of off-the-shelf or “pre-customized” packages. Yes, they do limit IC designers’ flexibility somewhat, but the significant savings in development time and engineering cost, as well as lower manufacturing cost will reward IC Vendors and OSATs royally for streamlining/automating their collaboration. Best of all, ADKs and Reference Flows make IC package design and manufacturing very scalable!!!
[post_title] => Collaboration Flow for Moore’s Law versus More than Moore
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eFPGA is now widely available, has been used in dozens of chips, is being designed into dozens more and it has an increasing list of benefits for a range of applications. Embedded FPGA, or eFPGA, enables your SoC to have flexibility in critical areas where algorithm, protocol or market needs are changing. FPGAs can also accelerate many workloads faster than processors. For example, Microsoft Azure uses one FPGA accelerator for every 2 Intel Xeons. Flex Logix provides eFPGA cores which have density and performance similar to leading FPGAs in the same process node. The EFLEX eFPGA is silicon proven in 40nm down to 12nm with 7nm in process.
WEBINAR: eFPGA What’s Available Now, What’s Coming & What’s Possible!
In this webinar Andy Jaros talks about the emergence of eFPGA over the last five years and the success of Flex Logix amongst multiple market segments. Here is a quick update from their website:
"We are solidly funded and backed by strong Venture Capitalists Lux and Eclipse. We have proven our eFPGA technology in 180nm, 40nm, 28/22nm, 16nm and 12nm with TSMC and GlobalFoundries. There are more than 10 working SoCs with our technology and >>10 more in fab/design. Our customers are very well funded organizations and companies and our technology is strategically critical to them. Our cash in the bank and our backlog/commitments mean that we do not need to raise cash in 2020 and we can fund our AI Inference chip development and production ramp from cash flow. Our AI chip, InferX X1, benchmarks with superior price/performance on real-world neural network models customers have given us. As X1 ramps production our financial situation will be even stronger."
Andy Jaros is one of my trusted few. He is the VP of Sales and Solutions Architecture at Flex Logix. Andy has more than 30 years of semiconductor experience most of which involves IP, most notably ARC, Virage Logic, and Synopsys. I was at Virage when we acquired ARC and that is where I first met Andy, who is also a neighbor of mine. He continued on with Synopsys after they acquired Virage and then moved to Flex Logix more than 4 years ago. At that time eFPGA was just another acronym. Today, Flex Logix is the leading provider of embedded FPGA hard IP and software. Flex Logix is also launching Inference Acceleration chips for Edge Applications so they are not just an IP company.
Flex Logix came to SemiWiki four years ago and we have now published 40 blogs with them that have earned more than 250,000 views. Excellent content gets excellent views, absolutely.
The webinar is coming up so register now:
WEBINAR: eFPGA What’s Available Now, What’s Coming & What’s Possible!
Here are the questions I have for Andy. If you have others let me know:
What is the area penalty for using an eFPGA?
How does the eFPGA get programmed and by who?
What specific design considerations do you need to make for eFPGA use?
[post_title] => eFPGA - What’s Available Now, What’s Coming and What’s Possible!
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On May 15th TSMC “announced its intention to build and operate an advanced semiconductor fab in the United States with the mutual understanding and commitment to support from the U.S. federal government and the State of Arizona.”
The fab will run TSMC’s 5nm technology and have a capacity of 20,000 wafers per month (wpm). Construction is planned to start in 2021 and production is targeted for 2024. Total spending on the project including capital expenditure will be $12 billion dollars between 2021 and 2029.
This announcement is undoubtedly the result of intense pressure on TSMC by the US government and it is also coming out today that TSMC will stop taking orders from Huawei also under pressure from the US.
What does this fab announcement mean?
This announcement is in my opinion soft, “Intention to build”, “construction planned to start”, “production targeted”. The project is based on a “mutual understanding and commitment to support from the U.S. federal government and the State of Arizona”, What happens if Donald Trump is voted out in November or just changes his mind? I could easily see this project never materializing due to changes in the US political situation or lack of follow-through from TSMC who is likely not excited about it to begin with.
My company IC Knowledge LLC is the world leader of cost and price modeling of semiconductors and MEMS. I thought it would be interesting to use our Strategic Cost and Price Model to make some calculations around this fab.
TSMC operates four major 300mm manufacturing sites in Taiwan and one in China. The four sites in Taiwan are all GigagFab sites, Fab 12, Fab 14, Fab 15 and Fab 18 are each made up of 6 or 7 wafers fabs sharing central facility plants. This Gigafab approach is believed to reduce construction costs by about 25% versus building a single stand-alone fab. The china fab location is smaller with 2 fabs at one location but the fab was equipped with used equipment transferred from fabs in Taiwan because the fab is trailing edge. If TSMC really builds a single US fab running 20,000 wpm the resulting cost to produce a wafer will be roughly 1.3% higher than for a GigaFab location due to higher construction costs. I believe it is unlikely the site will be equipped with used equipment transferred from Taiwan. The cost to build and equip the fab for 20,000 wpm should be approximately $5.4 billion dollars.
Locating a fab in the US versus Taiwan will result in the fab incurring US labor and utility costs, this will add approximately 3.4% to the wafer manufacturing cost.
The capacity of the fab is also smaller than a “typical” fab at advanced nodes, the three 5nm fabs TSMC is operating or planning for Taiwan are all 30,000 wpm. A 20,000 wpm fab will have an approximately 3.8% increase in costs versus a 30,000 wpm fab under the same conditions.
In total, wafers produced at the TSMC Arizona fab will be approximately 7% more expensive to manufacturer than a wafer made in Fab 18 in Taiwan. This does not account for the impact of taxes that are likely to be higher in the US than in Taiwan.
In the announcement TSMC has said the total spending on the project between 2021 and 2029 would be $12 billion dollars. That leaves money for a future expansion or conversion to 3nm. That would be almost enough money to add a second 20,000 wpm fab running 3nm as one possible example.
In summary the “announced” fab would likely be TSMC’s highest cost production site. It will be interesting to see if the fab materializes.
[post_title] => Cost Analysis of the Proposed TSMC US Fab
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[post_content] => Mutation testing is an intriguing idea, but is it useful? Paul Cunningham (GM of Verification at Cadence), Jim Hogan and I continue our series on novel research ideas, here looking at a paper examining the pros and cons of this topic. Feel free to comment if you agree or disagree.
The Innovation
This month’s pick is Which Software Faults Are Tests Not Detecting? The paper was presented at the 2020 Evaluation and Assessment in Software Engineering conference. The authors are all from Lancaster University in the UK.
The contribution in this paper is analysis of testing efficiency in software, to find methods to improve the ability of tests to uncover more bugs. The authors measure efficiency through a combination of code coverage and mutation analyses. In mutation testing functional errors are inserted in the code, testing is re-run and test efficiency is determined by ability to detect the mutation. They apply their analysis to 10 open-source systems with associated unit tests, using a tool to automatically insert faults. From this they analyze efficiency of the tests by fault type.
They report that in 6 of the systems, less than 50% of the injected faults are detected and some fault types are detected more frequently than others, particularly conditional boundary checks. They also find that the lowest performing tests are 10X less efficient in detecting boundary faults.
The authors also discuss challenges in mutation testing. One study finds that most post-release faults are complex and can only be fixed through modifications in several locations. Attempting to model these through mutation would explode rapidly. Also, a study at Google confirms that even simple mutation testing is very expensive. Many mutants are unproductive, being either redundant or equivalent, yet are not easily weeded out.
Paul
This is something we’re looking at closely as a natural area of interest in our metric driven verification (MDV) strategy. We’re always interested in ways to help improve test effectiveness; this paper adds to our understanding.
Testing mutated code is computationally expensive, whether it’s software or hardware, since you have to run all your tests not only on the original code but also on each mutated version. In hardware verification, testing the non-mutated design is already swamping verification resources. If we are going to do mutation testing in hardware, we need to focus on high ROI mutations. A second concern is that mutation testing exposes limitations in tests, not bugs in the design. Which is still valuable but not a first-order concern, making it a tougher sell for schedule-constrained projects.
Nevertheless, selective use of high ROI mutation coverage could still be helpful in hardware, especially for modules where there is no good functional coverage model available. The paper cites boundary condition mutation, for example, mutating “<=” with “<” as more likely to find useful gaps in tests than mutating “+” with “-“. Buffer overflow security attacks are given as a good example where boundary condition mutation can catch gaps in test suites. This example applies equally to both software and hardware test.
Very thought-provoking.
Jim
The observation I want to make here, as an investor is that I have seen a decline in research in functional verification at the RTL level, at least judging by the number of papers we see. Not application-level stuff, how to better use the tools we’ve already got, that’s common. I’m talking about original research, from universities or outfits like Google.
This isn’t because all the problems are solved – they definitely aren’t. I think it’s more for universities because grants are directed to problems in other areas, and in the hyperscalars because software is their biggest driver for innovation. What then should we do in functional verification for hardware? Learn from research in software verification! The two domains are very closely related, not identical but the overlap is significant. I want to see more of these software parallels.
On this topic specifically, I want to better understand the associated costs. That’s a huge factor in ROI; the “R” will have to be equally impressive.
Me
Security seems like a good application for mutation testing. Here there may be more willingness to accept the added overhead, also the recently released Mitre list of common weaknesses in hardware should provide inspiration for more security-related high-value mutations beyond boundary conditions.
To see the previous paper click HERE.
[post_title] => Is Mutation Testing Worth the Effort? Innovation in Verification
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Hours after agreeing to build a fab in US TSMC will stop selling to Huawei- Repercussions will reverberate through all tech: Semis, semi equip, chip customers, all collateral damage.
It has been reported by Nikkei and other sources that TSMC has stopped taking orders from Huawei in order to comply with US export controls.
HUAWEI CRACKDOWN
This comes literally hours after TSMC agreed to build a fab in the US. While this does not impact chips in the production process or already ordered it does stop new business . The Commerce initiative sets a hard deadline of September 14th to cut off business. This suggests that Huawei likely has at least 3-4 months or so before the impact will start to limit business. They likely have been stockpiling chips in anticipation of such a move.
A "virtual" death sentence for Huawei-
Much like we saw Jinhua die almost over night after the supply of US technology was stopped, it is clear that Huawei will no longer be competitive in the market against either Apple or Samsung in mobile phones and severely hampered in their network equipment side.
While Huawei will obviously try to shift chip production to Chinese suppliers and SMIC to fabricate the chips, SMIC is hindered in that it is several generations behind TSMC and its supply of EUV tools from ASML has also been cut off by the US.
It will take a while for the impact to be felt as Huawei has stocked up and chips are still in process but in a few months time those supplies will dry up and leading edge product will become unavailable.
We don't think that this is a negotiating ploy by the current administration...it feels too real this time. Even though there is time to negotiate yet another deal, we don't see the administration relenting before November as they want to be seen as hard on China both in retribution for Covid and less than successful trade deals.
Every US chip company will get hurt
Every US semiconductor Company from Intel and Qualcomm down to the smallest analog maker will be negatively impacted as China will go so far out of its way to avoid "buying American". Without doubt they will use inferior, trailing technology from inside China or other sources rather than rely on unreliable US made components that could be shut off at any moment.
China can't turn to Samsung
Even though Samsung's foundry division would love to get Huawei's business, it isn't going to happen. Number one, Samsung is obviously a competitor to Huawei in the handset business and number two, Samsung would never risk its semiconductor production to US sanctions, which is its life blood and the vast majority of its profitability.
This is of course aside from the fact that South Korea is very reliant on the US versus North Korea
US chip equipment sales to China will be cut
We were amazed that both KLA and AMAT blew off the embargo risk to China as if it was nothing by saying that they will just ship equipment from another country...no big deal...we can easily get around the restrictions. It was even more amazing that allegedly intelligent analysts on the call didn't question this and just accepted it.
While shipping US know how, technology and IP from another country where the last screw is installed in the equipment may comply with the letter of the law as it stands today (which is unclear at best) its obviously in clear, blatant opposition of the spirit of the law which is to deny US technology to companies that supply Huawei (read that as any China based chip company).
This loophole will be closed and may already be closed if you read documents from the commerce department.
Commerce Addresses Huawei's Efforts to Undermine Entity List, Restricts Products Designed and Produced with U.S. Technologies
Federal Register Language
Semiconductor equipment sold by AMAT, KLA & Lam, among others, even if manufactured, in whole or in part, outside the US , still clearly contain "US software & technology" which is the key target of restrictions by the US commerce department. The target of the restrictions is not where its made but what it contains.....
This means that semiconductor equipment companies entirety of business with China, ranging from 25% to 50% of revenues in some cases is at risk. This also includes sales to multi nationals who have a fab in China (including Intel, Samsung and others) not just indigenous fabs.
TSMC was forced to choose sides and picked the US
Like two primary school dodge ball teams choosing players for their side going after the best player available, TSMC was stuck in the middle and didn't want to upset either the US or China. The US stepped up the pressure by threatening to cut off TSMC's "oxygen" in the form of semiconductor equipment and TSMC quickly capitulated by not only announcing a fab in the US (even though its a token, show fab) but much more importantly blowing off their second biggest customer after Apple...Huawei. All of this knowing full well that this would turn into a major political football with China being a short sail away from Taiwan.
Its not like TSMC (or Taiwan for that matter) had much choice. Either embrace the US fully or just surrender today to China and hand over the keys to the island and the fabs to the "barbarians at the gate".
Others will be forced to choose sides as well. The US dodgeball team already has the Dutch and sooner or later Japan and Korea chip companies will have to choose sides. Israel is already there. The US has already been playing a "warm up game" in pressuring foreign countries on Huawei made networking gear.
The stocks and the fallout-----both ugly
Chip companies have a huge amount of business in China as China makes 70% of the worlds electronics goods. Apple is a top target, Boeing, even Tesla could be targeted.
Semiconductor equipment companies will lose business not shipped by Sept 14th and more in the long term as China steps up its efforts to be independent.
The impact won't be felt in the June quarter, nor the September quarter but the December quarter will be off a cliff.
In a perverse way, near term business will actually be up significantly as Chinese companies rush to get any chips and equipment into the country before the Sept 14th deadline. This means June and September could be better for Chinese business than expected.
Long term damage has already been done. Lots of losers....
Unfortunately, even if the US and China could patch things up by some miracle, which isn't happening any time soon, the long term damage has already been done.
China will rightfully triple down on becoming chip independent from the US and US companies will lose more business than ever.
Right now US/China tensions are very high but we are the two largest trading partners in the world and still do billions in business per day.
This will trickle down through Taiwan, the South China sea, Europe, Africa and beyond.
The global economy needs this like another hole in its head after getting whacked by Covid.
This increases our view that the fall is going to be very, very ugly for chips due to both the trickle down of the economic slowdown coupled with China trade problems....the "double, super duper, whammy"
[post_title] => TSMC stops doing business with Huawei!
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[post_content] => The road to a truly usable design management solution for electronic design has been a long and twisty one. Initially just handling EDA tool data was a struggle, let alone addressing mutli-user and multi-site needs. Of course, all along every EDA tool development company was internally using software revision control, which worked fine for source code, but was not efficient or practical for large binary files produced by layout tools, etc. The first generation of usable design management tools came as ad hoc vendor specific solutions that were part of the EDA frameworks. They suffered from lack of scalability and being vertical silos for each vendor. However, they did usually offer the advantage that they understood the library, cell, file schema of the underlying designs.
To break the log jam, it would take software companies that specialized in revision control, project management and more. Rational Software was an early leader in revision control for software development and other types of design management. Their innovative solutions were used outside of EDA for a long time. Because of their high performance and scalability, they made inroads into flows based on HDLs and firmware. However, a solid solution for analog and custom design waited until about 8 years ago when they developed a Cadence integration.
Along the way the ClearCase software moved between several different companies. Most recently it was owned by IBM. In 2016, seeking to accelerate development, IBM announced a partnership transferring development to HCL Technologies. This has ensured the proper level of resources and focus for the ClearCase offerings.
It’s easy to see why Cadence users would like the Flexiem design management solution from HCL based on ClearCase. It takes only seconds for a user to create a workspace where they can start working on and accessing everything needed for a design. Even though the design data may reside on multiple servers in local or remote locations, the Multiple Version File System (MVFS) creates a virtual file system where every file is immediately referenceable. Unmanaged files can easily be created and then checked in to make them managed.
Most importantly, Flexiem offers tight integration within the Cadence environment. Design views can be checked in and out within the Library Manager. The Flexiem integration with Cadence understands the design hierarchy and even is aware of schematic level changes between versions. With these features it is easy to check in or out complete design hierarchies in one step.
Because ClearCase is used widely within many enterprises, using it for design management harmonizes well with existing infrastructure. Flexiem also offers a rich and sophisticated access control system which is vitally important for managing who can see and/or make changes to design data. One benefit of this is the ability to protect and track internal and external IP. As hinted to above, the Versioned Object Bases (VOBs) for a design can be local, remote or distributed in a manner that is transparent to the user. Similarly, users can work in teams across geographic boundaries.
The overall level of capabilities that can be provided by a system as mature as the ClearCase based Flexiem would simply be impossible for an EDA vendor to develop. Flexiem is also tool vendor agnostic, so it can fit into flows with a wide variety of tools.
HCL has produced a video that will provide an overview of Flexiem as used for EDA design management. If you want more information, this video would be a good starting off point. Having worked with many design management systems over my career, I can say that the offering from HCL hits the sweet spot in term of performance, usability and maturity.
[post_title] => HCL Offers Tightly Integrated Design Management Solution for Virtuoso
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ANSYS is the world leader in engineering simulation across multiple markets. One of those markets just happens to be semiconductor which is why ANSYS is on SemiWiki.com. Due to the pandemic ANSYS has transformed their popular live regional events to one broad virtual event “Simulation World”.
“Simulation World is world’s largest virtual event for research and development leaders and engineering simulation thought leaders and users across industries. Through a series of informative keynote presentations, industry and initiative breakout sessions, attendees will learn the latest innovations and best practices in simulation and its application in sectors ranging from automotive to semiconductor to health care. Interactive chat features will help attendees connect in real time with their colleagues around the world to ask questions and to network. And they can learn about the newest advances in simulation from leading company in a partner pavilion.”
There are four semiconductor tracks including four designer presentations which is something ANSYS is well known for with live events such as the Design Automation Conference. Talking about products is one thing, talking about real problems those products solve is quite another, absolutely.
Here are the customer presentations:
Nitin Navale, CAD Manager, Xilinx Session title: Elastic Compute Scalable Design Methodologies for Next-Generation FPGAs Wednesday, June 10
Dai Dai, Mixed Signal Design Manager, NVIDIA Session title: Optimizing Electromagnetic Crosstalk and Power Distribution for HighSpeed Serial Links on Silicon Wednesday, June 10
Jiaze Li, Senior Engineer, Qualcomm Session title:Novel RTL Power Regression and Minimization Workflow for Mobile GPU Cores Thursday, June 11
Erman Timurdogan, Director, Analog Photonics Session title: Designing Large-Scale Silicon Photonics Integrated Circuits through PDK Component Library Thursday, June 11
You will also want to catch John Lee's keynote:
John Lee, Vice President and GM, Semiconductor BU Session title: Reducing Your Project Risk in a Time of Great Change Wednesday, June 10
For those of you who don't know John he is an EDA legend in the making. John started his career Co-founding Performance Signal Integrity, a startup from Carnegie Mellon University. Avant! acquired PSI in 1994 which is where I first met John. Avant! was acquired by Synopsys in 2002. John went on to Co-found Mojave Design, which Magma acquired in 2004, Magma and was acquired by Synopsys in 2012. John then assembled a team that built the first big data platform for chip design which was acquired by ANSYS in 2015.
Bottom line: When John speaks you listen, absolutely.
And what simulation event would not include academic research:
Sung-Kyu Lim, Professor, Georgia Tech Session title: Thermal Issues and Solutions for 3D ICs: Latest Updates and Future Prospect Thursday, June 11
Makoto Nagata, Professor, Kobe University Session title: A C-P-S Simulation Technique of Power-Noise Side Channel Leakage in Cryptographic Integrated Circuits Thursday, June 11
To round things out the ANSYS staff of experts weigh in:
Ankur Gupta, Senior Director, Application Engineering Session title: Not Your Dad’s Power Integrity Analysis Wednesday, June 10
Anand Raman, Senior Director, Key Global Accounts Session title: Top Electromagnetic Coupling Issues to Watch Out for in High Frequency Silicon Design Wednesday, June 10
Karthik Srinivasan, Sr. Manager, Product Management Session title: Designing High-Speed Memories for the Edge Without Falling Over the Edge Wednesday, June 10
Karan Sahni, Director, Applications Engineering Session title: All things 3D-IC: Taking the Headache out of Managing Multiphysics Codesign for a 3D-Chip Package-System Thursday, June 11
Remember, it is a virtual event so register now and you will get a link to the replay in case you miss it. The SemiWiki bloggers will be all over this event so stay tuned for our expert observations, opinions, and experience on the subject matters.
I hope to virtually see you there!
[post_title] => The Largest Engineering Simulation Virtual Event in the World!
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ANSYS is the world leader in engineering simulation across multiple markets. One of those markets just happens to be semiconductor which is why ANSYS is on SemiWiki.com. Due to the pandemic ANSYS has transformed their popular live regional events to one broad virtual event “Simulation World”.
“Simulation World is world’s largest… Read More
If you are like me, you will get a 5G phone because of the high bandwidth it offers. However, there is a lot more to 5G than just fast data. In fact, one of the appealing features of 5G is low bandwidth communication. This is useful for edge devices that perform infrequent and low volume data transfers and depend on long battery life. Prior… Read More
I’ve talked before about how Defacto provides a platform for scripted RTL assembly. Kind of a rethink of the IP-XACT concept but without need to get into XML (it works directly with SV), and with a more relaxed approach in which you decide what you want to automate and how you want to script it.
They’re hosting a webinar on May 28th 10-11am… Read More
If you’re not dizzy from all the changing market projections lately, you soon will be. At times like this, I believe it’s important to keep perspective and look beyond the next 24-hour news cycle to try and understand what the future holds. I’m happy to report there’s a great event coming up in June that will do just that.
The Silicon… Read More
The current Coronavirus crisis is inflicting a lot of pain on people, companies, and governments. I hope I am not getting in trouble with my reasoning, but if you look closely, there are also some “positives” to the Covid-19 crisis.
– It is stress-testing our infrastructure and telling us where we need to improve – as country,… Read More
eFPGA is now widely available, has been used in dozens of chips, is being designed into dozens more and it has an increasing list of benefits for a range of applications. Embedded FPGA, or eFPGA, enables your SoC to have flexibility in critical areas where algorithm, protocol or market needs are changing. FPGAs can also accelerate… Read More
On May 15th TSMC “announced its intention to build and operate an advanced semiconductor fab in the United States with the mutual understanding and commitment to support from the U.S. federal government and the State of Arizona.”
The fab will run TSMC’s 5nm technology and have a capacity of 20,000 wafers per month (wpm). Construction… Read More
Mutation testing is an intriguing idea, but is it useful? Paul Cunningham (GM of Verification at Cadence), Jim Hogan and I continue our series on novel research ideas, here looking at a paper examining the pros and cons of this topic. Feel free to comment if you agree or disagree.
The Innovation
This month’s pick is Which Software … Read More
Hours after agreeing to build a fab in US TSMC will stop selling to Huawei- Repercussions will reverberate through all tech: Semis, semi equip, chip customers, all collateral damage.
It has been reported by Nikkei and other sources that TSMC has stopped taking orders from Huawei in order to comply with US export controls.
The road to a truly usable design management solution for electronic design has been a long and twisty one. Initially just handling EDA tool data was a struggle, let alone addressing mutli-user and multi-site needs. Of course, all along every EDA tool development company was internally using software revision control, which … Read More
Scalable NoC, SoC and associated Testbench generation using Defacto STAR
eFPGA what’s available now, what’s coming & what’s possible?
ESD Protection Network Verification Using Magwel’s ESDi for HBM Simulation
Securing Your SoCs: Advanced Techniques for Security Verification
Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff
High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers
The processor at the heart of this Subsystem is the ARC EM11D. It combines high efficiency control with ultra low power DSP operations. Its ARC Processor EXtension (APEX) mechanism is useful for adding application specific extensions in the form of hardware RTL. It features a single cycle 16+16 MAC that efficiently supports PHY data processing. There is also a development library with rich DSP functions.
The NB-IoT subsystem has many features that enable low power communications. The Digital Front End facilitates integration with RF transceivers. Viterbi and trig functions are handled in hardware through APEX instructions. There are standard AHB/APB busses that help with SoC integration. There are also standard peripheral interfaces that can be used for power management, as well as RF and host connectivity. The subsystem also possesses flexible power management features with customer programmable power modes.
Rich talks about the needs of a complete IoT SoC using their IP based system concept. The IoT comms subsystem is combined with tRoot HSM for iSIM to provide SIM functionality and security. An RF transceiver, such as the Palma Ceia PCS NB-IoT Transceiver, eFlash and RAM/ROM round out the system, providing everything needed for a fully functional IoT SoC that can use 5G networks and have standby battery life of over 10 years.
At the end of the webinar Rich discusses a demo platform they assembled that shows the feasibility of the complete solution. 5G NB-IoT will be used in medical/fitness devices, smart cities, smart agriculture, industrial automation and many other applications. With the roll out of 5G, NB coverage will be available in places that never had low cost and low power service. There is rapid adoption in the US, Europe and Asia. Undoubtably there will be a high demand for SoCs that support NB-IoT. I’d suggest the Synopsys/Palma Ceia webinar video to anyone who has an interest in this topic. 
If you’re not dizzy from all the changing market projections lately, you soon will be. At times like this, I believe it’s important to keep perspective and look beyond the next 24-hour news cycle to try and understand what the future holds. I’m happy to report there’s a great event coming up in June that will do just that.
The Silicon Valley chapter of SEMI is presenting a webinar entitled: 
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Cost Analysis of the Proposed TSMC US Fab