Architecture Exploration of Processors and SoC to trade off power and performance 5

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                    [post_date] => 2021-05-03 06:00:52
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                    [post_content] => The evolution of low-cost heterogeneous multi-chip packaging (MCP) has led to significant system-level product innovations.  Three classes of MCP offerings have emerged:
  • wafer-level fan-out redistribution, using reconstituted wafer substrates of molding compound as the surface for interconnections between die (2D)
  • a separate silicon-based interconnect layer for redistribution, either a full-sized silicon interposer or die-to-die silicon bridges embedded in the organic package (2.5D)
  • face-to-face or face-to-back die stacked vertically, utilizing hybrid bonding of die pads, with through-die vias (3D)
The 2.5D solution has received considerable R&D investment, to support larger package sizes and greater interconnect redistribution density (i.e., line + space pitch, number of metal layers).  The integration of multiple, smaller die provides chip and package assembly yield and cost tradeoffs. The functionality integrated in the 2.5D MCP has become increasingly diverse – e.g., CPUs, GPUs, memory (especially HBM stacks), FPGAs, network switches, I/O transceivers, hardware accelerators for specific applications.  Current R&D efforts will continue to extend the breadth of this system-in-package composition – the next “big thing” could likely be the integration of optoelectronic conversion elements, enabling the efficiencies of photonic-based data transfer over medium- and short-range lanes. A key facet to enabling the growth of 2.5D MCP offerings is the technology for the internal connectivity between die in the package.  As mentioned above, one alternative is to fabricate the wires on a silicon interposer, whose dimensions equate to the full package size.  Recent advances have enabled interposers to exceed the 1X maximum reticle size for die placement and interconnect.  Another is to fabricate a small silicon bridge for the wires, embedded in an organic package, spanning the edges of adjacent die. Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) is an example of 2.5D MCP bridge interconnect technology.  It has been briefly described in previous SemiWiki articles (link). With the recent re-introduction of Intel Foundry Services, I thought it would be appropriate to dive a bit more deeply into this technology, as it will no doubt be a fundamental part of ICF customer system implementations. I had the opportunity to learn more about EMIB capabilities and potentials, in a most enlightening discussion with Ravi Mahajan, Intel Fellow in Assembly and Test Technology Development.  This article summarizes the highlights of our discussion. EMIB Fabrication EMIB cross section2 The figure above illustrates a cross-section of a typical EMIB bridge resident in the organic package.  The bridge silicon resides in a package cavity, fabricated as depicted in the figure below. The top package metal layer provides a reference plane, with vias through the plane connecting the die and bridge. package fabrication   Ravi indicated, “The EMIB process is built upon the standard package construction flow, with the additional steps to create the EMIB cavities.  The bridges are positioned in the cavities, held in place with an adhesive.  The final dielectric and metal build-up layers are added followed by via drilling and plating.” Note in the cross-section picture above the reference to coarse and fine vias, corresponding to the two different bump pitches present on each die, as shown below. fine coarse bumps The coarse bumps are used for die-to-package trace layer connections, while the fine pitch is associated with the EMIB connections – more on the target EMIB connection density shortly. Ravi added, “Considerable engineering effort was invested to define the fine and coarse bump profiles that would support die attach and via connection processing.  Specifically, that included focusing on bump height control and solder volume.  We have worked with bumping providers to enable this dual pitch and profile configuration.  In addition, each die in the MCP package is attached individually – the bumps on the die will be subjected to multiple reflow cycles.  Attention was paid to the flux materials incorporated with the bumps.  A process to provide void-free epoxy underfill throughout the bump regions has also been developed.  The materials, bumps, and the attach process are all in high volume manufacturing.” EMIB Physical Implementation An example of a fabricated bridge is shown below.  This specific design implements the following:
  • 55um bump pitch to the die above
  • 2um line + 2um space, with 2um metal thickness
  • 4um pitch, with 250 wires per mm “beachfront”
  • 2um thick dielectric between each EMIB metal layer
  • 4 metal layers on the EMIB bridge, M1 and M3 are dedicated to GND planes
  • signal layers that typically utilize a 3 signal + 1 ground shield pattern on M2 and M4
EMIB 3S1G cross section To be precise, the metal planes on the alternate EMIB layers are implemented as a mesh, as depicted below. shielding Ravi said, “The design of the EMIB interconnects is an intricate tradeoff between multiple targets – the interconnect density (wires per die edge per mm, bumps per mm**2), power constraints, and signaling bandwidth.  For each die, that implies driver sizing and receiver sensitivity.  For power savings, an unterminated receiver is typically used (i.e., capacitive load only, no resistive termination).  To address those targets, the EMIB design considerations include line and space dimensions, bump pitch, channel length, metal thickness, and dielectric material between the metal layers.  The design of the electrical signal shielding (e.g., S1G1, S2G1, S3G1) is also crucial.” The figure below shows the layout view of the interconnect density design, including how the bridge signals reach multiple rows of fine-pitch bumps on adjacent die.  The table below illustrates the range of dimensions and pitches available. interconnect density EMIB capabilities The figures below show various bridge positioning options.  Note that there is considerable flexibility in bridge placement – e.g., horizontal and vertical orientations, asymmetric locations relative to die edges. EMIB configurations EMIB Electrical Characteristics Intel has published a detailed electrical analysis for the EMIB interconnect, evaluating insertion loss and crosstalk for various signal-ground shielding combinations and wire lengths. (References appended at the end of this article.) power distribution The figure above highlights the power distribution paths in the package.  Note that the small footprint of the EMIB bridge means the balance of the I/O signal and power integrity characteristics are unaffected, unlike a full silicon interposer where all signal and power vias must first traverse through the interposer.  As mentioned earlier, the top package layer above the EMIB serves as a ground plane, as well. The figure below shows an example of the electrical analysis results, depicting the maximum EMIB signal length for a target cumulative beachfront bandwidth for various signal shielding patterns.  Aggressive L/S wire pitch designs were assumed for this example.  The electrical model used:
  • a simple output driver (R=50ohms, C=0.5pF)
  • an unterminated receiver (C=0.5pF)
  • four-layer EMIB metal stack-up, dielectric constant=4.0
  • top package metal plane above the embedded bridge
  • a 1V signal swing with a 200mV vertical eye opening receiver sensitivity (incorporating the near-end and far-end crosstalk for the unterminated, capacitive receiver)
datarate versus channel length EMIB Design Services Due to the intricacies of the EMIB design tradeoffs, Ravi indicated, “Intel will collaborate closely with the foundry customers on their product requirement, and develop the EMIB designs as a service.  We will work with the customers on die pinout and bump patterns, and provide the EMIB silicon implementations that address their datarate targets.”  EMIB layouts services EMIB Future Development EMIB technology continues to be an R&D focus at Intel.  Ravi highlighted, “We will continue to work on providing greater interconnect edge density, including tighter bump pitch and more aggressive line/space EMIB metal pitch (sub-1um).  It’s certainly feasible to incorporate active circuitry into the EMIB, as well.” Summary The EMIB bridge approach in support of advanced MCP technology offers some unique advantages:
  • extension of existing organic packaging technology
  • enables large die count and large package configurations
  • lower cost than a full-size silicon interposer
  • support for high datarate signaling between adjacent die, using simple driver/receiver circuitry
  • ability to optimize each die-die link individually by customizing the bridge for that link
The EMIB links are power-efficient, with low metal R*C delays, with minimal latency and high signal integrity. There are some EMIB disadvantages, which have been addressed by the Intel R&D team:
  • additional complexity in the die bumping and package assembly process
  • disparate coefficient-of-thermal-expansion (CTE) factors between the package, the die, and the EMIB bridge
The EMIB silicon is thinned prior to package assembly (t < 75um), and thus doesn’t significantly alter the thermally-induced mechanical strain between package and die and the bumps plus underfill interface.  The overall reliability is comparable to a conventional organic package. The support provided by the packaging team at the Intel Foundry Services will assist customers seeking advanced MCP solutions to achieve their signaling datarate, power, and cost targets. The growth of MCP packaging adoption will no doubt continue to accelerate.  (The DARPA CHIPS program will also contribute to greater interest in MCP design.) For more information on Intel’s EMIB offerings, please follow this link, and be sure to consult the references below. -chipguy   References [1] Mahajan, R., et al., “Embedded Multi-Die Interconnect Bridge (EMIB) – A High Density High Bandwidth Packaging Interconnect”, 2016 IEEE 66th ECTC conference, p. 557-565. [2]  Durgun, A., et al., “Electrical Performance Limits of Fine Pitch Interconnects for Heterogeneous Integration”, 2019 IEEE 69th ECTC conference, p. 667-673. [3]  Mahajan, R., et al., “Embedded Multidie Interconnect Bridge – A Localized, High-Density Multichip Packaging Interconnect”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 9, No. 10, October, 2019, p. 1952-1962. [post_title] => Intel’s EMIB Packaging Technology – A Deep Dive [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => intels-emib-packaging-technology-a-deep-dive [to_ping] => [pinged] => [post_modified] => 2021-05-03 14:40:46 [post_modified_gmt] => 2021-05-03 21:40:46 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=298674 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [1] => WP_Post Object ( [ID] => 298633 [post_author] => 14 [post_date] => 2021-05-02 10:00:08 [post_date_gmt] => 2021-05-02 17:00:08 [post_content] => KLAC Foundry Logic KLA - KLA put up an excellent quarter and Guide - Rising above the increasing tide of orders - Confirms $75B capex in 2021 with upside - Foundry & Logic continue to be the sweet spot for KLA Business is very very good and getting better -Revenues came in at $1.8B with EPS of $3.85, all above the range -Guidance is for $1.855B+-$100M with EPS of $4.08/ These are superb numbers any way you look at it. - Gross margin was at 62.9% and operating margin of 40.4% - $585M or 97.8% free cash flow conversion KLA remains a stand out leader in process control with 53% market share Both wafer inspection and patterning were up over a third from last year. Surprisingly Korea was 31% versus Taiwan's 22%. The only light area was process equipment which was up only 12% Y/Y, which trailed the market as compared to KLA's core business. Benefit from EUV rollout continues KLA continues to see increased business as EUV rolls out at different customers. KLA's 5th generation tools are adopted to help with the increasing roll out. In our view, the good order news coming out of ASML for tools translates a little bit later to more process control tools for KLA. In our view KLA always tends to follow in the footsteps of ASML's order pattern and it looks very strong. $75B in WFE capex for 2021? KLA management suggested that WFE spend in 2020 was about $61B and that 2021 would be up in the low to mid twenties we we take to mean about $75B. This is more or less in line with what we and the rest of the industry are initially thinking. We could see that number finish up higher but right now its a good number to use. KLA benefits from strong Foundry/Logic As we have said many times before, KLA is the poster child for foundry/logic spend and that is what we are seeing right now. While memory remains OK, foundry/logic is out performing and will continue to outperform given the perceived shortage and secular growth drivers. Memory may come back in the latter part of the year, maybe..., but for now it remains in the sweet spot of KLA's business model Financial performance remains top in the sector As compared to the rest of the semiconductor equipment group KLA remains the top performer on all financial metrics. Aside from the fundamental growth in the stock price, everything is as good as it gets. KLA retains its ATM machine like cash behavior which is reflected in the stock price. The Stock The stock traded down slightly in the after market despite the fantastic report. As we had projected earlier, there was a high degree of pressure and burden on KLA to put in performance that was well above and beyond expectation. The problem is that expectation has been growing by leaps and bounds and grew to an unreachable point in our view. It was all but impossible to get to a number that would make the street happy. In general, we think the group as a whole is at a point where the valuations have to take a rest and catch up with themselves. Valuations are priced well beyond perfection so perfect performance isn't good enough. We might look for entry points to get in the stock if we had some weakness or other non company specific down drafts. [post_title] => KLAC- Great QTR & Guide- Foundry/logic focus driver- Confirms $75B capex in 2021 [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => klac-great-qtr-guide-foundry-logic-focus-driver-confirms-75b-capex-in-2021 [to_ping] => [pinged] => [post_modified] => 2021-05-02 10:15:56 [post_modified_gmt] => 2021-05-02 17:15:56 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=298633 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [2] => WP_Post Object ( [ID] => 298665 [post_author] => 15 [post_date] => 2021-05-02 06:00:22 [post_date_gmt] => 2021-05-02 13:00:22 [post_content] => After I published a recent article about Intel, I was contacted by the Irish Development Agency (IDA) where Intel has a large fab presence and asked if I would like to interview them about the Intel site. The interview with Turlough McCormack of the IDA, started with Intel’s presence in Ireland but then went on to paint an interesting picture of a country successfully attracting high technology companies. I thought this is interesting not only for what it offers high tech companies but also as a model for the US. Intel in Ireland Intel has had a presence in Ireland for 32 years. Intel has 360 acres of land in Leixlip, a town near Dublin and from 1989 to 2015 Intel spent 8 billion euros on the site and between 2019 and 2021 is investing an additional 7 billion euros for a total investment of $15 billion euros. The site currently employs around 5,000 people and will reach around 6,600 people with the new investment. The latest investment will double Intel’s manufacturing space in Ireland, be a centerpiece of Intel’s 7nm manufacturing and be the most advanced fab in Europe. Figure 1 summarizes the Intel Ireland site.

Slide1 2

Figure 1. Intel Ireland

Ireland’s High-Tech Model After discussing Intel’s presence, we went on to discuss what makes Ireland attractive for high-tech in general and wafer fabs in particular. There is a lot of discussion going on in the US and Europe about our reliance on Asia in general and Taiwan in particular, for advanced semiconductors. Taiwan is in the middle of a drought and has been dealing with limited water availability for years not to mention being located on an earthquake fault line and the political uncertainty of their relationship with mainland China. Turlough pointed out it rains a lot in Ireland and there is no shortage of water, they also have plenty of power and broadband availability. Ireland is not on a fault line, has no natural disasters and a mild climate. I am also fairly sure England has no plans to invade Ireland unlike mainland China who regularly threatens Taiwan. The Government of Ireland has a pro-business attitude and has for many years. As a small country companies have access to key decision makers. Ireland has one of the lowest corporate tax rates in the world at 12.5%. Ireland has an open border policy and is actively trying to attract technical talent to the country with fast-track work permit programs. The government, universities and science centers are all working together on research initiates and developing talent. The Science Foundation Ireland is funding research in semiconductors and photonics at the university of Cork. With Brexit, Ireland is the only English-speaking country in the European Union and provides a gateway to Europe. Figure 2 summarizes Irelands pro high-tech environment.

Slide2 2 Ireland

Figure 2. Ireland High-Tech Model.

There are approximately 70 semiconductor companies with a presence in Ireland accounting for over 9,000 jobs and over 14 billion euro a year in 2018 revenue. The 70 semiconductor companies include around 24 smaller Irish companies and 300 million euro of R&D. Just in the last 12 months announcements have been made for:
  • Microchip R&D center in Cork providing 200 jobs.
  • Qualcomm 78 million euro R&D and chip design center.
  • Huawei 80 million euro investment that will result in 110 jobs
In the last few years Cadence, Maxim Integrated and Logitech have invested in Ireland. I also brought up Analog Device presence in Ireland is I believe their largest manufacturing site. He noted ADI has been in Ireland for 40 year and has employs around 1,000 people in Limerick. Interestingly, although the US invests more capital into Ireland than Irish companies do into the US, Irish companies employ more people in the US than US companies do in Ireland. He pointed out that Ireland is enabling US companies’ expansion into Europe, not taking US jobs. Conclusion In conclusion, Ireland has positioned their country as a business friendly, English speaking gateway to Europe. I believe that a lot of their business friendly policies would be useful additions to US policy to in our drive to increase US based leading edge semiconductor manufacturing. [post_title] => Ireland – A Model for the US on Technology [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => ireland-a-model-for-the-us-on-technology [to_ping] => [pinged] => [post_modified] => 2021-05-05 19:46:54 [post_modified_gmt] => 2021-05-06 02:46:54 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=298665 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 5 [filter] => raw ) [3] => WP_Post Object ( [ID] => 298391 [post_author] => 28 [post_date] => 2021-04-30 10:00:11 [post_date_gmt] => 2021-04-30 17:00:11 [post_content] => Dan and Mike are joined by Simon Butler, founder of Methodics and Brad Hart, CTO of Perforce. We explore the acquisition of Methodics by Perforce, including motivation, strategy and a look to the future. We also discuss some of the history of Methodics and how they became successful. For further discussion, visit their blog The Future of Semiconductor Design. Simon Butler General Manager, Methodics Business Unit Simon Butler was founder and CEO of Methodics Inc, acquired by Perforce in 2020, and is currently the General Manager of the Methodics Business unit at Perforce. Methodics created IPLM as a new business segment in the enterprise software space to service the needs of IP and component-based design. Simon has 30 years of IC design and EDA tool development and specializes in product strategy and design. Brad Hart Chief Technical Officer As the CTO of version control, Brad is responsible for the product strategy of the Perforce version control product suite – including Helix Core, Helix4Git, Swarm, and other clients and plugins. Brad has more than 20 years of experience in high-tech companies focused on optimizing development pipelines. He specializes in software engineering process, design, and implementation. The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual. [post_title] => Podcast EP18: The Story Behind Combining Methodics and Perforce [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => podcast-ep18-the-story-behind-combining-methodics-and-perforce [to_ping] => [pinged] => [post_modified] => 2021-05-05 18:52:49 [post_modified_gmt] => 2021-05-06 01:52:49 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?post_type=podcast&p=298391 [menu_order] => 0 [post_type] => podcast [post_mime_type] => [comment_count] => 0 [filter] => raw ) [4] => WP_Post Object ( [ID] => 298454 [post_author] => 28 [post_date] => 2021-04-30 06:00:52 [post_date_gmt] => 2021-04-30 13:00:52 [post_content] => Rich Weber SemiforeRich Weber co-founded Semifore in 2006 with Jamsheed Agahi. Rich has a long history of complex chip and system design at companies including Data General, Stardent, Silicon Graphics, StratumOne and Cisco Systems. He received an MS in Electrical Engineering and a BS in Computer Engineering from the University of Illinois, Urbana-Champaign. Rich’s pioneering work at Cisco formed the basis of what became the SPIRIT / Accellera SystemRDL1.0 standard in 2009. Rich is a long-standing member of the Accellera IEEE 1685 IP-XACT steering committee. He has a deep understanding of industry standards, including their limitations. What drove you to form Semifore in 2006? I’ve been responsible for system architecture throughout my career – things like how the hardware interacts with the operating system and embedded software. In virtually every project, I was the system architect responsible for defining the address map and how device drivers would interact with it across many different operating systems. My experience with all those projects led me to conclude that the hardware/software interface, let’s call it the HSI, was a source of significant risk in the development process. I can recall working at Silicon Graphics on high-end graphics processors and supercomputers. Often, there would be a fire drill in our Monday morning meeting because someone changed a bit in one of the registers and all the regressions failed over the weekend. At that point, the documentation was out of synch with the design RTL and many header files were likely incorrect. Those changes were made with good intentions, but the result was always the same – chaos. After that, I began working on high-performance networking designs at a startup. These designs had a much more complex HSI, probably a factor of ten times more complex than what I had seen at Silicon Graphics. Based on that, we decided to automate HSI generation – the RTL, design descriptions, verification files, device driver development and support for bench measurements.  The HSI represented a large portion of the design, so this automation had far-reaching impact on the overall project. In those days, there was no commercially available tool to perform this automation, so roughly half the effort of the design team was dedicated to building the necessary scripts. This company was quite successful and ultimately bought by Cisco. Now, as part of Cisco, the networking designs we were working on became much larger. In those days, Cisco had a specific focus on engineering best practices to reduce re-spins and time-to-market for its complex ASICs. Since Cisco was the result of many acquisitions, there was a need to converge the design methodology at an enterprise level. As part of that effort, I championed the need for an automated system to guide the implementation of the HSI. This part of the design had clearly become much too large and complex to be done either manually or with ad-hoc scripts and spreadsheets. A project to address this automation was created. While the work had a positive impact on the design projects at Cisco, I saw an opportunity to do so much more. Handling complex designs with large register counts is virtually impossible without sophisticated automation. I knew I could build such a system that would scale efficiently for the largest designs. Without such a system it is very likely there would be missed deadlines, late tape-outs and hidden bugs in the field. In fact, studies have shown that one out of seven chips are re-spun due to a problem with the HSI. So, I left Cisco and formed Semifore. Tell us about Semifore, what is the impact of their products on chip design? Advanced semiconductor designs have many components, including multi-core architectures, programmable peripherals and purpose-built accelerators. These design elements require a pathway for embedded software to communicate with them. This is the HSI and it forms the foundation for the entire design project. Building an HSI that is correct and reliable puts demands on many parts of the design team. Beyond building an accurate, robust register map, the validation of the interface needs to be complete, and all supporting information also needs to be complete since the software team will build device drivers and high-level firmware from these specifications. The stakes are quite high regarding getting all these pieces done correctly. Unlike timing or power closure, which can be verified rigorously, the verification of the HSI is a multi-dimensional problem that is bounded only by the imagination of the software team. I have seen cases where, years after a chip was put into production, it became impossible to add a new feature.  Why? During the software update process, it was discovered a device driver couldn’t be written. This was because a subtle error in the address map didn’t allow for the functionality. This is something of a nightmare scenario since the only fix is to deploy a new version of the chip to all systems in the field needing the new feature. Subtle errors can escape into production. The only viable way to minimize this risk is to build an HSI with robust automation to ensure a correct-by-construction result. Add to that automated and accurate dissemination of the information needed by all members of the design team and you have a winning methodology. This is the methodology delivered by Semifore. Scalability is another real problem for this kind of methodology. A typical HSI may contain millions of registers. The design team will require updates to these registers often, many times a day for example. The process of generating all this information needs to be extremely efficient, or the whole system will collapse under its own weight. The Semifore methodology can generate a five million register HSI in a matter of minutes. Problem solved. This is the mission of Semifore. Deliver a winning methodology to allow design teams to focus on innovation, knowing the HSI is complete, robust and well-understood by everyone. The result is significantly lower risk, improved time-to-market and superior performance. In fact, without a methodology like this the chances of a working design are quite low. A final question – How does Semifore fit with existing standards? Standards provide great benefit. We fully support these efforts at Semifore, and I’ve personally been involved in the development of many standards. But standards cannot realize the ultimate goal, which is to develop an executable specification of the design. An executable specification is the only way to capture design intent and ensure a correct-by-construction HSI. Design teams maintain specifications in formats such as SystemRDL, IP-XACT and large spreadsheets. These are all useful, but individually and even together they are missing many of the constructs needed to create a true executable specification and this is why standards fall short. Let me give you some examples. Moving up the level of abstraction and letting tools do the heavy lifting delivers a great productivity boost. To do this, programming constructs such as IF statements, LOOPS and CASE statements are needed, but they aren’t supported by existing standards. Often, the design may require a certain structure be imposed on a set of registers and the structure be captured in memory instead of flip flops. This is what is referred to as virtual registers. This is also not supported by existing standards. To address these requirements, Semifore developed a domain-specific language called CSRSpec™. This language supports all the constructs mentioned and many, many more. It evolves with design requirements in real time, whereas a standard language would take years to encapsulate new requirements. CSRSpec includes over 200 unique properties and 6,000 register behavior combinations and complements existing standards and adds many more needed capabilities, so design intent can be accurately captured to create that all-important executable specification. The CSRCompiler™ system generates high quality synthesizable RTL and all the support files needed to build the complete HSI and associated software drivers. CSRCompiler supports customization with a robust output tailoring capability that doesn’t require scripting. Through many years of development, CSRCompiler delivers extensive error checking and validation, with over 1,000 checks built in. All inputs are verified for semantic and syntactic correctness. Design practices that can lead to sub-optimal results are also flagged. This entire system can scale effortlessly to handle the largest, most complex designs. This is the winning methodology I referred to. It provides the margin of victory for Semifore’s many customers across a diverse set of disciplines. We support many promising startups and large enterprises such as Microsoft as well. I am very proud of our accomplishments and our growing customer base. [post_title] => CEO Interview: Rich Weber of Semifore, Inc. [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => ceo-interview-rich-weber-of-semifore-inc [to_ping] => [pinged] => [post_modified] => 2021-05-02 10:12:07 [post_modified_gmt] => 2021-05-02 17:12:07 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=298454 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [5] => WP_Post Object ( [ID] => 298446 [post_author] => 14 [post_date] => 2021-04-29 10:00:53 [post_date_gmt] => 2021-04-29 17:00:53 [post_content] => NASDAQ LRCX LAM - Business is about as good as it gets- $75B WFE in 2021? - China remains strong at 32% despite SMIC lack of license - NAND remains 48% of revs versus 31% foundry - DRAM steady @ 14% - Service was record $1.3B Strong results in a strong market Lam reported revenues of $3.85B and EPS of $7.49 for the March quarter, with record performance in many categories. Guidance was also strong at $4B +- 250M in revenues and $7.50 +- $0.50 in EPS. The stock was down in after market trading likely in part due to an interpretation of flattish guidance. We think its likely Lam being a bit more conservative as is usual for them Lam remains a "memory" poster child Memory was 62% of Lam's business while foundry was half that at 31%. While its clear that the vast majority of shortage related spending will be on the foundry side we would not exclude Lam from getting its fair share of foundry business as well. Investors who may be concerned that Lam will not see as much benefit may be nervous but the results seem to belie that concern. A memory comeback in the second half? DRAM spending remains reasonable (as pointed out in our earlier note and ASML management earlier today). There likely remains room for more business there while NAND continues its strength for high aspect ratio etch for multi layer technology. Even with record NAND revenue, foundry revenue was a record as well. Service is large at $1.3B Confirming a trend we have been seeing with companies in the space the percent of revenue from "service" continues to climb. Older fabs and equipment are being pushed hard as are new tools. Customers don't want downtime and want to squeeze as much out of tools as is possible. This trend will help build a strong defense against the eventual down cycle which always follows these exuberant times. A fairly "boringly" good quarter despite Covid Other than shipping costs being high and overall capacity tight we don't see any problems caused by Covid or related supply chain issues. There was nothing remarkable other than the record performance in several categories. We think Covid issues are behind the industry for the most part and Lam does not have the supply chain issues of more complex technology like EUV. Share gains in dep and etch Management talked about share gains in both dep and etch and especially conductor etch. While good, they were not likely huge as we haven't heard of big "takeaway" wins it is more likely a case of customer mix. The stocks Lam's stock was off in the after market after having a strong day on the coat tails of ASML's good news which drove all the equipment stocks. The flattish guide likely weighed the stock down in the after market but we think that is likely prudent, conservative guidance. Concerns about having less benefit from foundry related chip shortage spend are somewhat real but its not like Lam is not getting its fair share of foundry spend. Lam remains a bit of a memory story which could develop more if DRAM comes back more. At this point we think the onus is on KLA which is the poster child for the foundry business who should echo strong foundry performance seen by ASML when they report the quarter. Following that AMAT is the house that built TSMC so they should also have a great quarter. [post_title] => Lam Research performing like a Lion - Chip equip on steroids [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => lam-performing-like-a-lion-chip-equip-on-steroids [to_ping] => [pinged] => [post_modified] => 2021-05-02 10:11:13 [post_modified_gmt] => 2021-05-02 17:11:13 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=298446 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [6] => WP_Post Object ( [ID] => 298251 [post_author] => 16 [post_date] => 2021-04-29 06:00:14 [post_date_gmt] => 2021-04-29 13:00:14 [post_content] => It would be nice if there were a pre-packaged set of assertions which could formally check all aspects of cache coherence in an SoC. In fact, formal checks do a very nice job for the control aspects of a coherent network. But that covers only one part of the cache coherence verification task. Dataflow checks are just as important, where many things can go wrong, such as unintended reads of stale data. And where performance bottlenecks will inevitably appear. Accelerating Cache Coherence Verification

The need for directed test

In other words, directed test verification is unavoidable, whether through simulation or emulation. So what? You have to create testbenches for lots of other verification objectives. This is just another testbench, right? But directed coherence testing can get very complicated very fast. First consider the most basic test: from a single processor in a single cluster, through coherent interconnect. Does the cache in the interconnect behave correctly? Returning the value in the cache if found there, otherwise falling through to the memory controller to collect that value from off-chip memory. Repeat for every coherent master on every coherent interconnect. Now get a bit more sophisticated. Two masters, maybe two CPUs, are reading and writing at the same time. Except they’re doing so on two separate coherent networks (which must be mutually coherent). CPU-A writes a value to a memory location in cache in its network, then CPU-B wants to read the equivalent location from cache in its network. Snooping should detect the change and ensure that CPU-B picks up the correct value. Does it? Repeat for every possible such sequence and every pairwise combination of who goes first and who goes second (or even at the same time)? Also permute in the slaves that also need to access memory.

Automating test generation

The number of combinations here could spin out of control very fast. Especially when you may have more than 1000 interfaces on the network, not uncommon in datacenter SoCs. This needs thoughtful planning. Avoid confusing interaction between bugs in multiple blocks, and run faster, by using VIPs for most blocks except the ones you want to include in a given test. Avoid having to test all N2+ combinations through a carefully considered plan to meet coverage. Which also means you need a way to automatically generate a series of tests in which first only A, B and C blocks are RTL and everything else is VIP. Then B, C and D are RTL and everything else is VIP. And so on. For each test you’d like to be able to draw on pre-defined coherency test sequences, either at the simple test level or at the system level. And monitors to check across interconnect ports. All ready to apply. All of this is provided through the VC SoC AutoTestbench, building tests starting from a DUT IP-XACT model (or Verdi KDB) and VIP IP-XACT models. Which can then feed into the SoC Interconnect Workbench. An automated workflow to run all those zillions of tests. Coverage can be monitored through a verification plan you can define in Verdi. Debug you handle through Verdi Protocol Analyzer. Here with a protocol view, a transaction view and some pretty sophisticated filtering to isolate what is happening in transactions and resulting memory values. This is where you would pick up those instances (hopefully few) of reading a stale value.

Performance testing

The last big verification objective is for performance. It’s nice that your system works well when unstressed, but what happens when you’re running at speed and there’s a lot of traffic churning through those coherent networks? Here Synopsys provides a capability called VC VIP Auto Performance which will generate traffic following the Arm Adaptive Traffic Profile. (You need to create a test profile as input to this tool.) Subsequently you can analyze for latency and bandwidth problems in Verdi Performance Analyzer. A very comprehensive solution for directed cache coherency testing, especially at the system level. Satyapriya Acharya (Sr. AE Manager at Synopsys) has created a recorded presentation on this topic, with more detail than I have provided. He wraps up with a discussion of how quickly this testing can be mapped over to ZeBu emulation, delivering a 10k performance speedup. [post_title] => Accelerating Cache Coherence Verification [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => accelerating-cache-coherence-verification [to_ping] => [pinged] => [post_modified] => 2021-05-07 15:37:23 [post_modified_gmt] => 2021-05-07 22:37:23 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=298251 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [7] => WP_Post Object ( [ID] => 298518 [post_author] => 19 [post_date] => 2021-04-28 10:00:55 [post_date_gmt] => 2021-04-28 17:00:55 [post_content] => Chip Shortage COVID 19 Unmasks Transit Gaps I haven’t traveled a lot during the COVID-19 pandemic, but I have flown a few times around the U.S. As a former frequent flyer I pride myself on anticipating most travel circumstances and not being surprised or blindsided, but two recent visits to Austin, Texas, changed that when I couldn’t find a rental car. It was just 12 months ago that rental car operators were stashing cars at baseball stadium parking areas and vacant lots as the travel industry came crashing to a halt. One might have thought that those same rental car companies would be licking their chops about now as flights fill up and travelers return. One would be wrong. The problem is that rental car companies liquidated large portions of their fleets, expecting to restore them after the pandemic passed. Just as U.S. consumers are emerging from their pandemic dormancy, with stimulus cash in hand and cabin fever on the brain, rental car companies are confronting the reality of a new car shortage as the supply of microchips for automobiles dries up. Press reports are spreading about travelers resorting to renting U-Haul trucks – a stopgap measure that is likely to flummox graduating college seniors and families in the process of spring and summer relocations. I have to smile to myself as I read these reports. Almost anywhere else in the world, a lack of available rental cars would be a nothing burger, a non-story. From Asia to Europe to South America, foreign travelers can ably get around with the aid of widely available public transportation or taxis. Who needs a rental car? The U.S. traveler is uniquely dependent, or perhaps reliant is a better word, on rental cars to get around. One might argue this is the result of the vast open spaces in the U.S. not served by public transit or the insistence on the “convenience” and independence enabled by a borrowed vehicle to get from place to place. The reality is that the country has a long history of hostility toward mass transit – with that hostility emanating from the oil and automotive industries and radiating through the political environment. Let’s consider the wider impacts of these circumstances. The few flights I have been on in the past 12 months have all been completely packed – with the exception of one Delta flight – United was not as generous or rigorous at preserving open middle seats during the pandemic. Packed flights means airfares are headed northward with rising demand, as has been widely reported. Combine steeper airfares, with limited or unavailable rental cars and you have a recipe for packed highways this summer as consumers opt for a glorious return to the open road with all of the accompanying risks. Those still flying will have options should they be unable to locate rental cars at their destinations. Uber and Lyft are likely to see a robust boost in demand – though these operators are facing their own challenges recruiting and retaining drivers who are suddenly able to find better employment opportunities as the economy stirs to life. Reports are already emerging of renewed interest in taxis and taxi operators are reporting a recovery in demand. Now they, too, must recruit drivers as many of their taxis are sitting idle after their drivers were beaten down and kicked to the curb by the predations of Uber and Lyft and the pandemic. Where Uber and Lyft are unable to fill the transportation gap, the car sharing sector remains vibrant. Turo and Getaround are seeing a resurgence and, despite the departure from the U.S. of Maven, Car2Go, and DriveNow, operators including Avis’ ZipCar, AAA’s Gig, PSA’s FreeNow, Hyundai’s Mocean, Toyota’s Kinto, and a dozen or more other local operators such as Blink’s BlueLA or Good2Go in Boston have arrived to fulfill local driving needs. The U.S. is at a strange transportation tipping point where the Federal government is seeking to simultaneously rebuild highways, tunnels, and bridges; rejuvenate mass transit; and modulate personal car use with miles-driven taxes – at a time when consumers are shifting away from mass transit and diving back into their cars to road trip. Concerns over emissions and climate change - reflected in proclamations at global summits and EV investments - appear to have taken a back seat to the call of the open road...which is not so open. The only saving grace is the growing population of workers indicating that they do not intend or would prefer not to return to commuting to the office. Meanwhile, due to the ongoing automotive chip shortage, demand for new and used vehicles is outstripping supply driving up new and used car prices. The winners in this emerging scenario will be ride hailing and car sharing operators, new and used car dealers, and the airlines and oil companies. The rest of us can expect a return to gridlocked highways and the familiar sticker shock on the dealer lot. What is new, though, is the almost complete absence of available rental cars. The lack of rental cars is a truly ominous turn – an unmasking of the vulnerability of the traveling public to the limitations of the automobile industry’s supply chain. This reality ought to motivate a reconsideration of the inadequacy of public transportation in the U.S. With the creation of the interstate highway system, inspired in large part by Germany’s Autobahn, the U.S. struck a deal with the oil and automobile industries. Now, we are confronting the limitations of vehicular travel based on individually owned cars and a failure to build out mass transit. The country is turning to electrification as the panacea to solve all automobile-based transportation woes, not recognizing that electrification brings its own challenges related to both supply chain and infrastructure issues. The evaporation of the rental car supply is a reminder that the real missing link in U.S. transportation is a comprehensive network of mass transit joining up highway, rail, and airport hubs. The Biden Administration’s emphasis on electrification ($174B) over mass transit ($30B) seems more than a little off kilter. Mass transit may not be sexy, but it is precisely because of the investments other nations have made in mass transit that a (presumably) temporary rental car shortage is a non-issue – that is, everywhere else but the U.S. where we have come to rely on the rental car. That dependence is a red flag that ought to be read as the white flag of surrender that it represents. COVID-19 and the automotive chip shortage have combined to send us a message that we have become and are becoming automobile dependent. This is a weakness that puts U.S. transportation in the category of a Third World country. If we are going to build back better, we ought to focus on fixing this first...with more money for mass transit. [post_title] => Chip Shortage, COVID-19 Unmasks Transit Gaps [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => chip-shortage-covid-19-unmasks-transit-gaps [to_ping] => [pinged] => [post_modified] => 2021-04-29 11:34:54 [post_modified_gmt] => 2021-04-29 18:34:54 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=298518 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [8] => WP_Post Object ( [ID] => 298357 [post_author] => 16 [post_date] => 2021-04-28 06:00:49 [post_date_gmt] => 2021-04-28 13:00:49 [post_content] => You might have heard of the Multicore and Multiprocessor SoC (MPSoC) Forum sponsored by IEEE and other industry associations and companies. This group of top-notch academic and industry technical leaders gets together once a year to talk about hardware and software architecture and applications for multicore and multiprocessor systems-on-chip (SoCs). They gather to debate the latest and greatest ideas to meet emerging needs. Kurt Shuler, vice president of marketing at Arteris IP, calls these meetings “The Davos for chips.” They’re held in some pretty nice locations around the world, and he tells me the food and wine at these events are also quite good! Arteris IP Contributes to Major MPSoC Text The forum will release a two-volume book to celebrate their 20th anniversary on May 11. You can buy this direct from Wiley, or you can pre-order on Amazon. The first book covers architectures, the second applications. The first book divides into sections on processor architectures, memory architectures, interconnects, and interfaces. K. Charles Janac, president and CEO of Arteris IP, wrote the first chapter in the third section on network-on-chip (NoC) architectures. I’m impressed that what must be considered a definitive technical reference on MPSoCs required a chapter on NoC interconnect, and the editors turned to Arteris IP to write that chapter.

Background

Let me start by emphasizing that these books are a technical reference without marketing or advertising, not surprising given the authors and publisher. Charlie’s chapter kicks off with some background on how chip connectivity has evolved from buses through crossbars to NoCs. I’ve talked about this in a previous blog. He then goes into detail that I think teams new to NoCs will find helpful — considerations in architecting and configuring the network. This spans from architecture to floor planning since you must consider quality of service (QoS) and additional services you must support like debug and safety. Floorplan efficiency is a key advantage for NoCs over crossbars. Naturally you should plan this into the implementation.

System-level Services

The most obvious service a NoC can provide is in guaranteed QoS. What may be less familiar to many is the degree of flexibility designers have in that management. You can manage performance statically or dynamically within the NoC or through software-based controls. Debug is another obvious service. Since the NoC sees all data traffic, designers can create probes to inspect data, monitor performance and generate traces for use by CoreSight and other debuggers. For safety-critical designs, the NoC must also provide support for FMEDA analyses. And for safety mitigation techniques like parity, ECC, duplication and TMR. A NoC can support system-level ISO 26262 ASIL D safety by connecting a safety monitor through the network to each IP and supporting the isolation of connected IP blocks to test those IPs while the design is active in an application. For security, NoCs provide firewalls with the same intent as network firewalls, blocking malware activity inside the chip.

Cache Coherence

I’ve written before about cache coherence support in SoCs. The size and complexity of modern SoCs, driven particularly by computer vision and AI, create a need for coherence across many IPs in the chip. Just think of an ADAS object recognition system with a video front-end. Now coherence must span many non-CPU IPs, distributed across a large die. That wide distribution demands NoC interconnect, which must also support cache coherence. Charlie goes into some details on the mechanism, protocols and messaging here.

Future Developments

NoCs have been doing very well in keeping up with these needs. So well that now they’re the leading interconnect option across the top semis and system builders in many applications. From mobile phones to TVs, cameras, cars, drones, remotes and high-performance servers. You’d be hard-pressed to find an advanced design that isn’t based on NoC technology. With this lead, NoC providers are being pushed to service  more new demands on interconnect. Among these, topology synthesis and floorplan awareness rank high. The bigger these SoCs become, the more NoC teams need automation to test topologies against trial floorplans. Proliferating AI architectures push the need for more creative interconnect options in grid-, ring- and torus-based accelerators. Broadcasting weights and aggregating reads across this architecture in one clock tick requires special support. AI already demands cache coherence support with the controller subsystem. Scalable accelerators want to rely on local cache coherence domains for 1, 2 or 4 accelerators at the top connecting to controllers. Making hierarchical cache coherence a reality. The ASIL D “fail-operational” mechanism I talked about earlier is going to grow. Who wants the whole SoC to fail if one subsystem fails? Remember when you had to restart your browser if one website locked up? That’s Stone Age – we expect modern browsers to be resilient to page failures. SoCs will go the same way. Now system builders want to move beyond error detection to prediction. Sound familiar? This further emphasizes the central role the NoC will play in an SoC, moving from a passive interconnect to the heart of communication, monitoring and control within the chip/3D stack/intelligent system. Well worth reading.     [post_title] => Arteris IP Contributes to Major MPSoC Text [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => arteris-ip-contributes-to-major-mpsoc-text [to_ping] => [pinged] => [post_modified] => 2021-05-07 15:36:52 [post_modified_gmt] => 2021-05-07 22:36:52 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=298357 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [9] => WP_Post Object ( [ID] => 298441 [post_author] => 14 [post_date] => 2021-04-27 10:00:14 [post_date_gmt] => 2021-04-27 17:00:14 [post_content] => ASML Stock Price 2021Taiwan and Korea represented 43% and 44% respectively with China at 15% and Japan and the US in the far distance. ASML a tidal wave of orders On the call management talked about logic potentially being up 30% in 2021 and memory being up potentially 50%. While we thing foundry/logic will clearly be on fir we think memory will lag a bit. Given that litho has the longest lead times of any semiconductor equipment tool, especially EUV, customers are clearly securing their place in line as quickly as they can. Litho systems are typically much of the bottleneck in a fab. Capacity constrained As we have previously mentioned, litho tools are a bit like 15 year old scotch in that the production pipeline is both very long and very limited. Perhaps the biggest limitation to increasing capacity remains the lens systems which take a very long lead time from partner Zeiss. Not only are the raw materials in short supply but there are just so many lenses that can be polished at the same time. At one point, years ago, there were a limited number of young east Germans who wanted to apprentice to learn how to polish glass for the rest of their lives. Now that the process is more automated the limitation is the number of custom built polishing machines which management pointed to on the call. Much like Scotch, there is not a lot that management can do to increase supply in the short term, the next 2-3 years, given the time and cost it would take to build out infrastructure. The other problem is that if you start spending on capacity infrastructure now, the shortage will likely be long over by the time it comes on line thereby creating and excess supply or wasted capacity spending. Basically you have to make calculated smaller increases in order to not overshoot the target (remembering that this is a cyclical industry no matter how much everyone tries to forget that) Software "quick fixes" Management did point to increased sales of software upgrades which do provide a painless quick hit to increase capacity somewhat. These are also important in that they do not take the tool down for long periods which would further exacerbate the capacity issue. The problem is that software is little more than a band aid and nothing replaces more litho tools. We could see similar software upticks at companies like KLA that offer multiple menus of upgrade options and additions to their tools that could help the yield curve and thus capacity. Positive collateral impact Its pretty clear that everyone in the semiconductor equipment food chain will see a lot more business in 2021. As usual, Litho leads the way, followed by process control followed by fabrication tools. We expect similarly positive outlooks fro Applied, Lam and KLA as well as TEL. The back end is already seeing an order jump with BESI showing a strong uptick. The stocks As we write this, ASML is up 3.5% along with most of the group up a similar amount. The stocks have recently had a bit of a pullback after a rip roaring run. Applied analyst meeting seemed to be the high water mark with things falling off after that. Earnings season with associated strong guidance may likely get us back on track if others follow ASML's lead as I expect will be the case. [post_title] => ASML early signs of an order Tsunami - Managing the ramp [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => early-signs-of-an-order-tsunami-managing-the-ramp [to_ping] => [pinged] => [post_modified] => 2021-04-28 10:54:48 [post_modified_gmt] => 2021-04-28 17:54:48 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=298441 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) ) [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object ( [ID] => 298674 [post_author] => 2635 [post_date] => 2021-05-03 06:00:52 [post_date_gmt] => 2021-05-03 13:00:52 [post_content] => The evolution of low-cost heterogeneous multi-chip packaging (MCP) has led to significant system-level product innovations.  Three classes of MCP offerings have emerged:
  • wafer-level fan-out redistribution, using reconstituted wafer substrates of molding compound as the surface for interconnections between die (2D)
  • a separate silicon-based interconnect layer for redistribution, either a full-sized silicon interposer or die-to-die silicon bridges embedded in the organic package (2.5D)
  • face-to-face or face-to-back die stacked vertically, utilizing hybrid bonding of die pads, with through-die vias (3D)
The 2.5D solution has received considerable R&D investment, to support larger package sizes and greater interconnect redistribution density (i.e., line + space pitch, number of metal layers).  The integration of multiple, smaller die provides chip and package assembly yield and cost tradeoffs. The functionality integrated in the 2.5D MCP has become increasingly diverse – e.g., CPUs, GPUs, memory (especially HBM stacks), FPGAs, network switches, I/O transceivers, hardware accelerators for specific applications.  Current R&D efforts will continue to extend the breadth of this system-in-package composition – the next “big thing” could likely be the integration of optoelectronic conversion elements, enabling the efficiencies of photonic-based data transfer over medium- and short-range lanes. A key facet to enabling the growth of 2.5D MCP offerings is the technology for the internal connectivity between die in the package.  As mentioned above, one alternative is to fabricate the wires on a silicon interposer, whose dimensions equate to the full package size.  Recent advances have enabled interposers to exceed the 1X maximum reticle size for die placement and interconnect.  Another is to fabricate a small silicon bridge for the wires, embedded in an organic package, spanning the edges of adjacent die. Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) is an example of 2.5D MCP bridge interconnect technology.  It has been briefly described in previous SemiWiki articles (link). With the recent re-introduction of Intel Foundry Services, I thought it would be appropriate to dive a bit more deeply into this technology, as it will no doubt be a fundamental part of ICF customer system implementations. I had the opportunity to learn more about EMIB capabilities and potentials, in a most enlightening discussion with Ravi Mahajan, Intel Fellow in Assembly and Test Technology Development.  This article summarizes the highlights of our discussion. EMIB Fabrication EMIB cross section2 The figure above illustrates a cross-section of a typical EMIB bridge resident in the organic package.  The bridge silicon resides in a package cavity, fabricated as depicted in the figure below. The top package metal layer provides a reference plane, with vias through the plane connecting the die and bridge. package fabrication   Ravi indicated, “The EMIB process is built upon the standard package construction flow, with the additional steps to create the EMIB cavities.  The bridges are positioned in the cavities, held in place with an adhesive.  The final dielectric and metal build-up layers are added followed by via drilling and plating.” Note in the cross-section picture above the reference to coarse and fine vias, corresponding to the two different bump pitches present on each die, as shown below. fine coarse bumps The coarse bumps are used for die-to-package trace layer connections, while the fine pitch is associated with the EMIB connections – more on the target EMIB connection density shortly. Ravi added, “Considerable engineering effort was invested to define the fine and coarse bump profiles that would support die attach and via connection processing.  Specifically, that included focusing on bump height control and solder volume.  We have worked with bumping providers to enable this dual pitch and profile configuration.  In addition, each die in the MCP package is attached individually – the bumps on the die will be subjected to multiple reflow cycles.  Attention was paid to the flux materials incorporated with the bumps.  A process to provide void-free epoxy underfill throughout the bump regions has also been developed.  The materials, bumps, and the attach process are all in high volume manufacturing.” EMIB Physical Implementation An example of a fabricated bridge is shown below.  This specific design implements the following:
  • 55um bump pitch to the die above
  • 2um line + 2um space, with 2um metal thickness
  • 4um pitch, with 250 wires per mm “beachfront”
  • 2um thick dielectric between each EMIB metal layer
  • 4 metal layers on the EMIB bridge, M1 and M3 are dedicated to GND planes
  • signal layers that typically utilize a 3 signal + 1 ground shield pattern on M2 and M4
EMIB 3S1G cross section To be precise, the metal planes on the alternate EMIB layers are implemented as a mesh, as depicted below. shielding Ravi said, “The design of the EMIB interconnects is an intricate tradeoff between multiple targets – the interconnect density (wires per die edge per mm, bumps per mm**2), power constraints, and signaling bandwidth.  For each die, that implies driver sizing and receiver sensitivity.  For power savings, an unterminated receiver is typically used (i.e., capacitive load only, no resistive termination).  To address those targets, the EMIB design considerations include line and space dimensions, bump pitch, channel length, metal thickness, and dielectric material between the metal layers.  The design of the electrical signal shielding (e.g., S1G1, S2G1, S3G1) is also crucial.” The figure below shows the layout view of the interconnect density design, including how the bridge signals reach multiple rows of fine-pitch bumps on adjacent die.  The table below illustrates the range of dimensions and pitches available. interconnect density EMIB capabilities The figures below show various bridge positioning options.  Note that there is considerable flexibility in bridge placement – e.g., horizontal and vertical orientations, asymmetric locations relative to die edges. EMIB configurations EMIB Electrical Characteristics Intel has published a detailed electrical analysis for the EMIB interconnect, evaluating insertion loss and crosstalk for various signal-ground shielding combinations and wire lengths. (References appended at the end of this article.) power distribution The figure above highlights the power distribution paths in the package.  Note that the small footprint of the EMIB bridge means the balance of the I/O signal and power integrity characteristics are unaffected, unlike a full silicon interposer where all signal and power vias must first traverse through the interposer.  As mentioned earlier, the top package layer above the EMIB serves as a ground plane, as well. The figure below shows an example of the electrical analysis results, depicting the maximum EMIB signal length for a target cumulative beachfront bandwidth for various signal shielding patterns.  Aggressive L/S wire pitch designs were assumed for this example.  The electrical model used:
  • a simple output driver (R=50ohms, C=0.5pF)
  • an unterminated receiver (C=0.5pF)
  • four-layer EMIB metal stack-up, dielectric constant=4.0
  • top package metal plane above the embedded bridge
  • a 1V signal swing with a 200mV vertical eye opening receiver sensitivity (incorporating the near-end and far-end crosstalk for the unterminated, capacitive receiver)
datarate versus channel length EMIB Design Services Due to the intricacies of the EMIB design tradeoffs, Ravi indicated, “Intel will collaborate closely with the foundry customers on their product requirement, and develop the EMIB designs as a service.  We will work with the customers on die pinout and bump patterns, and provide the EMIB silicon implementations that address their datarate targets.”  EMIB layouts services EMIB Future Development EMIB technology continues to be an R&D focus at Intel.  Ravi highlighted, “We will continue to work on providing greater interconnect edge density, including tighter bump pitch and more aggressive line/space EMIB metal pitch (sub-1um).  It’s certainly feasible to incorporate active circuitry into the EMIB, as well.” Summary The EMIB bridge approach in support of advanced MCP technology offers some unique advantages:
  • extension of existing organic packaging technology
  • enables large die count and large package configurations
  • lower cost than a full-size silicon interposer
  • support for high datarate signaling between adjacent die, using simple driver/receiver circuitry
  • ability to optimize each die-die link individually by customizing the bridge for that link
The EMIB links are power-efficient, with low metal R*C delays, with minimal latency and high signal integrity. There are some EMIB disadvantages, which have been addressed by the Intel R&D team:
  • additional complexity in the die bumping and package assembly process
  • disparate coefficient-of-thermal-expansion (CTE) factors between the package, the die, and the EMIB bridge
The EMIB silicon is thinned prior to package assembly (t < 75um), and thus doesn’t significantly alter the thermally-induced mechanical strain between package and die and the bumps plus underfill interface.  The overall reliability is comparable to a conventional organic package. The support provided by the packaging team at the Intel Foundry Services will assist customers seeking advanced MCP solutions to achieve their signaling datarate, power, and cost targets. The growth of MCP packaging adoption will no doubt continue to accelerate.  (The DARPA CHIPS program will also contribute to greater interest in MCP design.) For more information on Intel’s EMIB offerings, please follow this link, and be sure to consult the references below. -chipguy   References [1] Mahajan, R., et al., “Embedded Multi-Die Interconnect Bridge (EMIB) – A High Density High Bandwidth Packaging Interconnect”, 2016 IEEE 66th ECTC conference, p. 557-565. [2]  Durgun, A., et al., “Electrical Performance Limits of Fine Pitch Interconnects for Heterogeneous Integration”, 2019 IEEE 69th ECTC conference, p. 667-673. [3]  Mahajan, R., et al., “Embedded Multidie Interconnect Bridge – A Localized, High-Density Multichip Packaging Interconnect”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 9, No. 10, October, 2019, p. 1952-1962. [post_title] => Intel’s EMIB Packaging Technology – A Deep Dive [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => intels-emib-packaging-technology-a-deep-dive [to_ping] => [pinged] => [post_modified] => 2021-05-03 14:40:46 [post_modified_gmt] => 2021-05-03 21:40:46 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=298674 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [comment_count] => 0 [current_comment] => -1 [found_posts] => 7658 [max_num_pages] => 766 [max_num_comment_pages] => 0 [is_single] => [is_preview] => [is_page] => [is_archive] => [is_date] => [is_year] => [is_month] => [is_day] => [is_time] => [is_author] => [is_category] => [is_tag] => [is_tax] => [is_search] => [is_feed] => [is_comment_feed] => [is_trackback] => [is_home] => 1 [is_privacy_policy] => [is_404] => [is_embed] => [is_paged] => 1 [is_admin] => [is_attachment] => [is_singular] => [is_robots] => [is_favicon] => [is_posts_page] => [is_post_type_archive] => [query_vars_hash:WP_Query:private] => f6cf882a22c63d085e4467ee30435821 [query_vars_changed:WP_Query:private] => 1 [thumbnails_cached] => [stopwords:WP_Query:private] => [compat_fields:WP_Query:private] => Array ( [0] => query_vars_hash [1] => query_vars_changed ) [compat_methods:WP_Query:private] => Array ( [0] => init_query_flags [1] => parse_tax_query ) [tribe_is_event] => [tribe_is_multi_posttype] => [tribe_is_event_category] => [tribe_is_event_venue] => [tribe_is_event_organizer] => [tribe_is_event_query] => [tribe_is_past] => [tribe_controller] => Tribe\Events\Views\V2\Query\Event_Query_Controller Object ( [filtering_query:protected] => WP_Query Object *RECURSION* ) )

Intel’s EMIB Packaging Technology – A Deep Dive

Intel’s EMIB Packaging Technology – A Deep Dive
by Tom Dillinger on 05-03-2021 at 6:00 am

EMIB configurations

The evolution of low-cost heterogeneous multi-chip packaging (MCP) has led to significant system-level product innovations.  Three classes of MCP offerings have emerged:

  • wafer-level fan-out redistribution, using reconstituted wafer substrates of molding compound as the surface for interconnections between die (2D)
Read More

KLAC- Great QTR & Guide- Foundry/logic focus driver- Confirms $75B capex in 2021

KLAC- Great QTR & Guide- Foundry/logic focus driver- Confirms $75B capex in 2021
by Robert Maire on 05-02-2021 at 10:00 am

KLAC Foundry Logic

– KLA put up an excellent quarter and Guide
– Rising above the increasing tide of orders
– Confirms $75B capex in 2021 with upside
– Foundry & Logic continue to be the sweet spot for KLA

Business is very very good and getting better

-Revenues came in at $1.8B with EPS of $3.85, all above the range
-Guidance… Read More


Ireland – A Model for the US on Technology

Ireland – A Model for the US on Technology
by Scotten Jones on 05-02-2021 at 6:00 am

Slide1 2

After I published a recent article about Intel, I was contacted by the Irish Development Agency (IDA) where Intel has a large fab presence and asked if I would like to interview them about the Intel site. The interview with Turlough McCormack of the IDA, started with Intel’s presence in Ireland but then went on to paint an interesting… Read More


Podcast EP18: The Story Behind Combining Methodics and Perforce

Podcast EP18: The Story Behind Combining Methodics and Perforce
by Daniel Nenni on 04-30-2021 at 10:00 am

Dan and Mike are joined by Simon Butler, founder of Methodics and Brad Hart, CTO of Perforce. We explore the acquisition of Methodics by Perforce, including motivation, strategy and a look to the future. We also discuss some of the history of Methodics and how they became successful.

For further discussion, visit their blog TheRead More


CEO Interview: Rich Weber of Semifore, Inc.

CEO Interview: Rich Weber of Semifore, Inc.
by Daniel Nenni on 04-30-2021 at 6:00 am

Rich Weber

Rich Weber co-founded Semifore in 2006 with Jamsheed Agahi. Rich has a long history of complex chip and system design at companies including Data General, Stardent, Silicon Graphics, StratumOne and Cisco Systems. He received an MS in Electrical Engineering and a BS in Computer Engineering from the University of Illinois, Urbana-Champaign.… Read More


Lam Research performing like a Lion – Chip equip on steroids

Lam Research performing like a Lion – Chip equip on steroids
by Robert Maire on 04-29-2021 at 10:00 am

NASDAQ LRCX LAM

– Business is about as good as it gets- $75B WFE in 2021?
– China remains strong at 32% despite SMIC lack of license
– NAND remains 48% of revs versus 31% foundry
– DRAM steady @ 14% – Service was record $1.3B

Strong results in a strong market

Lam reported revenues of $3.85B and EPS of $7.49 for the March… Read More


Accelerating Cache Coherence Verification

Accelerating Cache Coherence Verification
by Bernard Murphy on 04-29-2021 at 6:00 am

Cache coherence checking min

It would be nice if there were a pre-packaged set of assertions which could formally check all aspects of cache coherence in an SoC. In fact, formal checks do a very nice job for the control aspects of a coherent network. But that covers only one part of the cache coherence verification task. Dataflow checks are just as important, where… Read More


Chip Shortage, COVID-19 Unmasks Transit Gaps

Chip Shortage, COVID-19 Unmasks Transit Gaps
by Roger C. Lanctot on 04-28-2021 at 10:00 am

Chip Shortage COVID 19 Unmasks Transit Gaps

I haven’t traveled a lot during the COVID-19 pandemic, but I have flown a few times around the U.S. As a former frequent flyer I pride myself on anticipating most travel circumstances and not being surprised or blindsided, but two recent visits to Austin, Texas, changed that when I couldn’t find a rental car.

It was just 12 months … Read More


Arteris IP Contributes to Major MPSoC Text

Arteris IP Contributes to Major MPSoC Text
by Bernard Murphy on 04-28-2021 at 6:00 am

Wileybook min

You might have heard of the Multicore and Multiprocessor SoC (MPSoC) Forum sponsored by IEEE and other industry associations and companies. This group of top-notch academic and industry technical leaders gets together once a year to talk about hardware and software architecture and applications for multicore and multiprocessor… Read More


ASML early signs of an order Tsunami – Managing the ramp

ASML early signs of an order Tsunami – Managing the ramp
by Robert Maire on 04-27-2021 at 10:00 am

ASML Stock Price 2021

Taiwan and Korea represented 43% and 44% respectively with China at 15% and Japan and the US in the far distance.

ASML a tidal wave of orders

On the call management talked about logic potentially being up 30% in 2021 and memory being up potentially 50%. While we thing foundry/logic will clearly be on fir we think memory will lag a bit.… Read More