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                    [post_content] => TSMC is the bellwether for not just the semiconductor industry but the worldwide economy. TSMC makes semiconductors, semiconductors are where electronics begin and electronics are the foundation of modern life, absolutely.

Apple is also a key economic indicator and as we all know Apple is a strategic partner of TSMC. The Apple TSMC relationship started with the iPhone 6 and other iProducts (20nm in 2014) and continues to this day. The recently introduced iPhone 12 is based on TSMC 5nm. Next year Apple will use an enhanced version of 5nm and in 2022 it will be 3nm.

TSMC raised its 2020 revenue forecast for a second time this year (10% -> 20% -> 30%) with strong demand for 5G and high-performance computing (HPC). The pandemic has resulted in a much stronger emphasis on mobile and cloud computing which should continue in Q4. IoT is also up but Automotive and DCE is down, again due largely to the pandemic. TSMC’s HPC (cloud) content will also benefit from additional AMD and Intel wafer agreements from 7nm down to 3nm over the next five years.

TSMC Revenue Comparison:

TSMC Revenue Analysis 2020

In my opinion AI and the cloud will be the key semiconductor drivers moving forward. Vast amounts of data is being generated by our electronic devices. The data is now moving to the cloud for harvesting and monetization. Cars are an easy example. I can assure you that Tesla will be using data from their cars to make more money than from the selling the cars. Think Google and search, Facebook and personal information, or Amazon and shopping, it is all about the data.

It's interesting to note the process node breakout:
38% of revenue is from mature CMOS nodes. Those nodes were cloned by UMC, SMIC, and GLOBALFOUNDRIES so there is strong competition where designs can be moved from one fab to another with relative ease. That is not the case with FinFET based designs so TSMC’s strong market position will continue to evolve in the future.

For 20nm and 10nm Apple was the only customer to hit HVM thus the shrinkage. TSMC moved 20nm fabs to 16nm and 12nm. The 10nm fabs were moved to 7nm and 6nm. Let’s call it the yield learning two-step where TSMC takes smaller process steps each year versus the much larger traditional semiconductor process steps.  For example, TSMC started EUV with a mature 7nm node then went full EUV at 5nm. Intel on the other hand is expected to go from zero EUV at 10nm to full EUV at 7nm.

Notable C. C. Wei quotes from the Q3 2020 Earnings Call:
"For TSMC, our technology leadership position enabled us to capture the industry megatrend of 5G and HPC. We expect to outperform the foundry revenue growth and grow by about 30% in 2020 in U.S. dollar terms."

"This is pretty hard for me to answer, because I cannot release all the information I got from my customer. But let me say that, on the average, the 5G phone have about 30% to 40% more silicon content as compared with 4G."

"We are complying full year with the regulations and so and we also notice that there is report saying that the TSMC got the (Huawei)  license. We are not going to comment on this unfounded speculation. And we also don't want to comment on our status right now. For the 4Q shipment to Huawei, the ban, the regulation already say that after September 17th, zero."

"Certainly TSMC is working with all the customers and view them as our partners. And so we don't using this opportunity to raise our 8" wafer price."

"We are engaging with more customer at N3 as compared with the N5 and N7 at the similar stage. So there's a lot of customers are working with us. And now, which one in the second half of 2022, which one would be the first product? Actually in smartphone and HPC applications, both."

Bottom Line: TSMC and the rest of the semiconductor ecosystem seems to be somewhat COVID resistant. The new "work and learn from home" life style is accelerating the digital transformation and that means more semiconductors now and in the future.

About TSMC
TSMC pioneered the pure-play foundry business model when it was founded in 1987, and has been the world’s largest dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.

TSMC deployed 272 distinct process technologies, and manufactured 10,761 products for 499 customers in 2019 by providing broadest range of advanced, specialty and advanced packaging technology services. TSMC is the first foundry to provide 5-nanometer production capabilities, the most advanced semiconductor process technology available in the world. The Company is headquartered in Hsinchu, Taiwan. For more information please visit https://www.tsmc.com.

 
                    [post_title] => TSMC Sets the Stage for a Great 2021!
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                    [post_content] => Paul Wells SemiWiki 1What brought you to semiconductors? 
As a kid I was interested in electronics and early personal computers. I went on to graduate from Manchester University in 1986, the birthplace of the modern computer, studying Computer Engineering where for my final year project I designed a gate array using Ferranti Electronics technology (1.2um!). After seeing the devices work first time, I was so enthused I went to work for them – they later became Plessey and then GEC Plessey (GPS). Joining Fujitsu I then became a logic designer using a new language called Verilog and an early version of design compiler. We developed a Speech Processor chip in 0.8um technology for a GSM chipset. Latterly I moved into the highly successful ASIC team as a physical design engineer supporting customers all over Europe and Israel – the 90’s were an exciting time as everything went digital. I joined my first start-up, Jennic, in 2000 where after a few iterations we transitioned to a fabless model designing and supplying wireless microcontrollers targeting the Zigbee standard. Here I built and led the operations team to deliver evaluation kits, modules and packaged devices to our end customers. A brief sojourn into digital TV followed where I spent 2 years working for Pace Networks managing a team of 70 to develop a mini headend (The MultiDweller) distributing HD video and data over cable networks. Following this I co-founded sureCore in 2011 with support from a tech savvy investor.

What is the sureCore company backstory?
After leaving Pace Networks in 2010 I was introduced to an investor keen to capitalise on the technology developed by a Glasgow University spinout called “Gold Standard Simulations” (GSS) led by Prof. Asen Asenov – a world leading expert on silicon process variability. Working with GSS highlighted the challenges of SRAM design for sub-40nm nodes – the industry was demanding increased on-chip SRAM but the density and power characteristics were no longer scaling at the same rate due to process variability. My colleagues in the industry confirmed that the underlying SRAM architecture hadn’t changed in over ten years. At sureCore we started to explore various architectural enhancements that could manage variability and cut power consumption. Working closely with ST we developed a test chip in 28FDSOI that showcased our technology by demonstrating power savings in excess of 60%. We were later able to prove that our circuit techniques were as applicable to both Bulk CMOS and FinFET processes.

What range of products do sureCore develop and what is their USP?
Our principal focus is on low power and low voltage SRAM. We have a product family called “PowerMiser” that typically delivers 50% dynamic power savings and about 20% static power savings compared to competitive offerings. Our “EverOn” family enables the SRAM to be directly interfaced to the logic without the need for level shifters and can operate from the process Vnom all the way down to the bit cell retention voltage. This is facilitated by our patented “SMART-Assist” technology. We have compilers for a range of nodes from 40nm to 22nm. We have also developed a range of low voltage register files that can similarly operate at extremely low voltages – allowing architects the capability to scale performance as the application requires and make significant power savings.

We also offer a custom memory development service called “sureFIT” where we work closely with our customers to understand their application and jointly come up with a memory specification that aligns with usage requirements and delivers an optimal power profile. For many customers seeking to deliver power optimised solutions, for example, in the medical, IoT or AI spaces then this service can help deliver truly differentiated products.

Why is SRAM power such a big deal?
The last ten years has seen a dramatic rise in the quantity of embedded SRAM on chip. For multi-processor devices integrating SRAM made sense as pulling code and data from off-chip DRAM had huge power and timing penalties. Over the last few years AI developers similarly looking for power optimisations have been driven to integrate many Mbytes of on-chip SRAM. Other application spaces like AR and Networking have comparable demands. Some market researchers estimate that SRAM occupies up to 70% die area for some applications and whilst this is not true across the board the underlying trend is clearly upwards. SRAM provides the fastest most efficient access to data, however, the power consumed contributes significantly to the overall consumption, in some cases limiting the maximum performance and in others meaning expensive package selection to ensure adequate thermal dissipation. Cutting SRAM power consumption is an area whose time has come and for which sureCore technology is ideally suited.

Does sureCore only focus on SRAM or are there other areas when you bring value?
Over the course of many years developing low power SRAM we have developed a range of low  power design methodologies and know-how that enable us to rapidly port between process nodes. We have also invested heavily in statistical and parametric verification capabilities as well as timing/power characterization. Some of our customers exploit these skills to help augment their own teams.

What can be done to optimize SRAM for particular applications?
Our optimizations are pretty much focused on power – whether that be dynamic or static. Power has become the critical issue for our industry whether to prolong battery life or to reduce power dissipation for thermal or cost reasons. For battery powered applications then it is all down to the usage profile. For those that spend most of their time asleep then clearly leakage is critical. For others in the medical space like hearing aids then not only is leakage important but also dynamic power. The capability to operate across a wide voltage range can yield spectacular power benefits. At sureCore we have developed a “tool-box” of power saving techniques that can be applied to any application. Early engagement by way of a feasibility study allows us to explore a variety of potential architectures that could suit the customers need. Once this is understood then a full implementation program can be scoped.

What customer problems have you solved thus far?
One customer we worked closely with needed a large multi-Mbyte memory subsystem for an AR application. Building this from off-the-shelf SRAM proved untenable from a system power budget perspective. By creating a custom SRAM instance and integrating it into a low voltage interconnect fabric meant power savings of over 40% could be achieved compared to a standard implementation. Also contributing to the power efficiency was an understanding of access patterns meaning that an intelligent access controller could keep most SRAM instances asleep until an access was due. This was implemented in a 16nm FinFET process.

Another customer in the networking space, also targeting 16nm, needed a 1-Write, 8-Read memory. By undertaking an architectural exploration we were able to demonstrate that the optimal solution was a double pumped implementation based on a custom 1-Write, 4-Read bit cell. The 8 reads being delivered by 2 reads per port per cycle. Not only did this meet area requirements it also delivered power savings of 60%.

What does the next 12 months have in store for sureCore?
The 16FF node is starting to be seen as a highly power efficient alternative. Although initially developed for high performance applications both density and leakage characteristics are making it increasingly attractive for a range of medical and wearable applications. The company is currently engaged with a tier-1 customer keen to exploit both our SRAM and register file technologies in 16FF. Previous projects have demonstrated that sureCore technology scales well to FinFET nodes and delivers significant power savings compared to competitors. By adopting our technology the customer will be able to deliver genuinely differentiated products with dramatic improvements in battery life. We intend to capitalize on this engagement and make it available across a range of advanced process nodes and foundries. Never has our industry needed a low power SRAM alternatively more desperately. We at sureCore intend to fill that gap.
                    [post_title] => CEO Interview: Paul Wells of sureCore
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                    [post_content] => TSMC ASML EUV 2020
  • ASML has strong quarter lead by great Taiwan and EUV
  • EUV "crossed over" DUV as revenue leader- signaling new era
  • Taiwan doubles, China grows, Korea weaker, US further behind
ASML hits great numbers ASML reported revenues of Euro 4B, with income of Euro 2.54EPS, both beating estimates handily. Ten EUV systems were shipped but 14 were recognized. Outlook is for revenues between Euro 3.6B-3.8B, which suggests upside to Euro 4B or better. Shifting Numbers There were significant shifts quarter over quarter. EUV went from 7 systems to 14 systems in Q3. Taiwan went from 21% of business to 47% with China going from 23% to 21% of business but increasing in absolute revenues. Korea slumped from 38% to 28% as EUV (which is not memory driven) dominated. The US (read that as Intel) fell off sharply fro.m 17% to 5%. Intel "crushed" by TSMC in EUV spend- a very bad leading indicator In the quarter Taiwan (primarily TSMC) was 47% of ASML's business while the US (primarily Intel) was a paltry 5%. This means that TSMC is spending more or less ten times what Intel is spending on EUV. In case there was any question as to who is winning Moore's law by a tidal wave of investments. Intel investors should be scared...very scared. Intel is clearly voting with their feet and matching their words about outsourcing their future to TSMC, who is running away in the Moore's law race. China spending four times what the US is spending (though none of it on EUV per the embargo) shows that China is deeply building out a strong semiconductor infrastructure and also clearly outspending the US. Logic dominates at 79% versus memory of 21% Logic at 79% is one of the highest percentages of revenues we have ever seen and is indicative of memory spending being subdued and perhaps weaker. The fact that this is so weighted to TSMC suggests that they are expecting a lot of business and also expect to put their foot on the EUV accelerator and leave both Intel and Samsung in their EUV dust. Memory obviously does not currently use EUV so the EUV domination of the current quarter will also outweigh memory DUV spend as ArF sales were down sharply. Some "pushouts" and timing issues in the future? A while ago we had talked about TSMC slowing spending and the pushouts and timing issues discussed on ASML's call are likely related to what we heard as we may see some digestion in 2021 after its gigantic spending binge in 2020 (not unlike Samsung's spending binge of a couple of years ago...). This talk of pushouts and timing may spook investors but fits the pattern of our suggestion that the COVID led technology, work from home, spending spree will slow as the economic impact of COVID finally trickles down to the semiconductor industry. Expect a lumpier business going forward Given the dominance of EUV with systems north of $100M, a few systems more or less can make the quarters lumpier. Customer timing, pushouts and node changes will all add to lumpiness. The reality is that the end game of EUV and High NA remains the same and remains very good. The road to EUV itself was obviously very lumpy with fits and starts so investors should understand this. We would try to take a longer term view, though that may be difficult, and look at longer term trends. Not much talk about "High NA" We think that now that EUV is commonplace, the next upside wave will be High NA which will likely be easier (on a relative basis) as compared to the original EUV roll out. We think the potential technology benefits as well as financial benefits may make High NA more attractive than the EUV model. But High NA is still a few years away..... Crossover from DUV to EUV - passing of the baton ASML has now officially crossed over from being a DUV dominated company to an EUV dominated company. This brings a different set of challenges but a welcome set. The key here is that they are the only EUV game in town so it cements their market share at virtually 100% versus having to compete (somewhat) at DUV. This makes the quite unique and valuable as compared to other semiconductor equipment companies who still slug it out in hand to hand battles. ASML is now "above the fray" The Stocks We don't expect much movement on ASML's stock price as it was already priced for the perfection we got. The talk of pushouts and timing may dampen sentiment and weigh on the stock and offset the positives. We do think it was prudent for management to keep expectations under control. At just over $400 per share ASML is not cheap nor expensive but appropriate given circumstances. Collateral Stock Impact In general we think that ASML's strong performance first out in the quarter bodes well for the semiconductor equipment industry. Our main concern is that the stocks remain ahead of reality. The weak memory showing could be interpreted as bad for memory centric players, most notably Lam (though we have heard they are doing just fine) EUV spend clearly helps KLA and to a slightly lesser extent Applied. Robert Maire [post_title] => ASML is Strong Because TSMC is Hot! [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => tsmc-is-hot [to_ping] => [pinged] => [post_modified] => 2020-10-20 11:40:37 [post_modified_gmt] => 2020-10-20 18:40:37 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292061 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 2 [filter] => raw ) [3] => WP_Post Object ( [ID] => 292026 [post_author] => 16 [post_date] => 2020-10-15 06:00:18 [post_date_gmt] => 2020-10-15 13:00:18 [post_content] => In the early days of Atrenta I met with Ralph Marlett, a distinguished test expert with many years of experience at Zuken and Recal Redac. He talked me into believing we could do meaningful static analysis for DFT-friendliness at RTL. His work with us really opened my eyes to the challenges that test groups face in integrating their highly complex additions into the mission mode RTL developed by the mainstream design group. Test is generally an independent team tasked with finding and working around test challenges in each new RTL drop. Typically in crazy short schedule allowances. One of those challenges that doesn’t get a lot of attention is the intersection between power management and test. Defacto has added power in test analytics to their tool suite in support of this need.

Why care about power in test?

Power-managed SoCs are typically designed with the assumption that they will never be on everywhere and clocking everywhere across the chip. That would be crazy – they would burn out right? But what about when the die/wafer is on a tester? Speed of test is paramount, so the default testing mode works directly against that power assumption. This means that test now also needs to become power aware. Scan chains have to understand power and DVFS domains for example. They have to be grouped in ways that are consistent with UPF-defined domains. For example, recognizing that scan chains running between different domains may require them to conflict with mean or peak power plans. Equally domain-switching signals must be accessible from the testing environment. Usually we think of the power state engine managing these exclusively (in turn also managed by software). But test needs a more direct handle on these controls. And of course test signals crossing between voltage domains need UPF commands for level shifters.

Automating test feasibility, adaptation

This stuff is all routine these days in mission mode RTL development, but test teams have expertise in test, not so much in power management, so they welcome help in navigating these new requirements. Defacto have stepped in to help test experts model the interaction between their test plans and the power architecture. Through the STAR platform, a test expert can stitch trial scan chains and trial power control overrides (in test mode) into the RTL. This after all is what Defacto do really well, incrementally modifying RTL to stitch in nets and instances. They can visualize how chains overlap power domains and how domain control signals interact with those domains. They can also auto-fix such cases. Power in Test at RTL A test engineer can model how all of this interacts with test compression for what-if analysis, varying the number of EDT channels and scan chains. Based on this, the Defacto flow will allow them to assess compression-aware test coverage estimates. They can dump that modified RTL, along with a testbench to drive scan testing. Which they can they run in their favorite simulator to validate test functionality. STAR DFT flow Defacto got their start in helping test engineers stitch test logic into design RTL, so this is a very natural advance for them to add, especially since the test experts already know and depend on their tools. You can learn more about Defacto here and you can see them at virtual ITC 2020 November 3rd-5th. [post_title] => Power in Test at RTL Defacto Shows the Way [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => power-in-test-at-rtl-defacto-analyzes-for-feasibility [to_ping] => [pinged] => [post_modified] => 2020-10-15 16:34:35 [post_modified_gmt] => 2020-10-15 23:34:35 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292026 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [4] => WP_Post Object ( [ID] => 291698 [post_author] => 11830 [post_date] => 2020-10-14 10:00:28 [post_date_gmt] => 2020-10-14 17:00:28 [post_content] =>

 

Concurrency and Collaboration – Keeping a Dispersed Design Team in Synch with NetAppIn a recent post, I discussed how NetApp provides comprehensive support for moving your EDA flow to the cloud. In that post, I explored the tools, technologies and services that help design organizations move to the cloud in a coherent, predictable, and incremental manner. Having a smooth-running hybrid/on-premise or fully cloud-based design flow is a necessary, but not sufficient condition for success. Coordination between the various parts of a geographically dispersed design team is critical as well and requires special tools and techniques. In this piece, I’d like to explore concurrency and collaboration with regard to how NetApp can keep a dispersed design team in sync.

The Problem

Almost any design project of a reasonable size is dispersed over multiple locations. This is a fact of life in our worldwide, connected community. While they are dispersed, all design teams need to collaborate and share data to meet aggressive project milestones. This sounds straight-forward, but it’s not. These teams will compete for on premise compute and storage resources as they will often have overlapping project schedules. Data concurrency is also a challenge. I can tell you from first-hand experience that keeping all team members working on the same version of the design isn’t easy. Also related to resource contention, burst storage and compute needs during peak load times make the whole problem more difficult.

Solution Requirements

There are several technologies and methods needed to address these challenges. Data must be available when and where it is needed, independent of geography. Design teams need to be able to effectively share data across multiple on-premise datacenters and the cloud. In general, a true hybrid-multi-cloud environment is needed to create a predictable schedule and a productive organization.

NetApp Technology

With this backdrop, let’s examine what NetApp brings to the table in the context of these real-world challenges. As discussed in my last post, NetApp is a force in data management for the EDA industry. The company has a rich set of capabilities for on premise and cloud requirements. Some relevant technology includes:

  • ONTAP: This is NetApp’s core storage operating system. It delivers an industry leading enterprise data management capability that is simple, flexible and secure with powerful capabilities, proven storage efficiencies and leading cloud integration
  • CVO: Cloud Volumes ONTAP facilitates the creation of your own custom, enterprise-grade environment on the cloud. It allows easy migration of capabilities from on premise environments to the cloud, with support for both
  • FlexCache: This is one the key building blocks for NetApp’s architecture. FlexCache is a remote caching capability that simplifies file distribution, reduces WAN latency and lowers WAN bandwidth costs. It enables distributed product development across multiple sites, as well as branch office access to corporate datasets
  • Snapmirror: This is another key building block. Snapmirror is a cost-effective, easy-to-use unified replication solution across the network. It replicates data at high speeds over LAN or WAN, delivering high data availability and fast data replication

Examples & Discussion

Mellanox uses NetApp’s Cloud Volumes ONTAP on Azure to create a hybrid cloud/on premise environment. This facilitates sharing data with multiple customers, which promotes innovation at the product level vs. needing to focus on the infrastructure. Looking inside the company, since Cloud Volumes ONTAP provides shared and accessible data, production engineers can review logs from all Mellanox factories and analyze them for insights. You can read more about how Mellanox uses NetApp here.

I’ve seen many geographically dispersed design projects over the years. Today, it’s almost impossible to find a project of any size or complexity that is located in one place. The challenge of ensuring each team member is working on the same, up-to-date version of the design has been around for quite a while. There is a relatively new challenge for large projects associated with effective use of on-premise infrastructure and the need to scale seamlessly to the cloud for burst needs while maintaining data and flow coherency. NetApp’s ONTAP storage operating system addresses the concurrency challenge and CVO/FlexCache works in all three of the leading cloud environments and on-premise.  This is how you achieve scalability and robustness.

NetApp unifies cloud and on premise

I’ll conclude with one more customer story. This one isn’t about chips, or even HPC systems. It’s about creating dragons and pandas at DreamWorks. The scale of the projects at DreamWorks will actually sound familiar. DreamWorks has over five billion digital files being developed in multiple overlapping projects, creating significant contention for datacenter resources.  NetApp enables DreamWorks to make data available in the right location at the right time to enable concurrent design, both on-premises and in the cloud at the same time. Without a sophisticated data management backbone, collaboration between animation teams would quickly become an exercise in data management vs. creativity. According to Skottie Miller, technology fellow at DreamWorks, “NetApp has managed data for every CG animated film that’s been produced at DreamWorks.”

You can learn more about how DreamWorks uses NetApp here.  There are many more compelling customer success stories, you can find more information on NetApp and its impact on customer projects here. Many of these stories have a common thread. To keep a large and distributed design team productive requires two primary technologies. First, efficient, distributed access to a single source of accurate data and second, the ability to scale the process seamlessly between on-premise and cloud to allow for rapid and cost-effective growth. NetApp provides both. So, when it comes to concurrency and collaboration, NetApp keeps a dispersed design team in sync.

[post_title] => Concurrency and Collaboration – Keeping a Dispersed Design Team in Sync with NetApp [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => concurrency-and-collaboration-keeping-a-dispersed-design-team-in-sync-with-netapp [to_ping] => [pinged] => [post_modified] => 2020-10-14 13:14:24 [post_modified_gmt] => 2020-10-14 20:14:24 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291698 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [5] => WP_Post Object ( [ID] => 291708 [post_author] => 23 [post_date] => 2020-10-14 06:00:31 [post_date_gmt] => 2020-10-14 13:00:31 [post_content] => We Dont Want IoT Cybersecurity Regulations It simply makes no sense to call for IoT devices to be certified safe-and-secure. Before you get bent out of shape, hear me out. Regulations are unwieldy blunt instruments, best left as a last resort. Cybersecurity regulations are not nimble, tend to be outdated the day they are instituted, and become a lowest-common-threshold for an industry to follow. This stifles security innovation and the application of best practices. On the upside, regulations do force industries that have ignored basic security practices to meet a common standard. But history has shown those industries rarely go any farther than the regulatory requirements. All the data breaches we see in the news every week, almost all of those organization are compliant with regulations, yet they are losing data records by the billions. Compliance does not equal security! Yet some are pounding the government drums, advocating for IoT certification regulations. I find their beliefs to be shortsighted and premature. Regulations are definitely needed in some situations, but only for narrow applications to accomplish specific goals. Protecting privacy of children online, securing sensitive healthcare records, or requiring controls around credit card transactions are all codified to some extent in regulations. I am a passionate security advocate, some would even go so far as to say a fanatic, but I don’t like this idea of requiring IoT devices to be certified safe and secure. It is simply too broad and undermines the economic model which is driving rapid innovation. We don’t require such certification for phones, tablets, personal computers, or servers. So why would anyone think requiring certification for low powered IoT devices is a good strategy? Certification adds significant costs and time to product development. IoT devices are emerging for a vast variety of uses and tend to be less expensive than fully-featured computing systems. The scale of validation is another problem as the number of IoT devices will soon exceed over 50 billion. The process to determine who will certify entirely new classes of devices and what criteria will be accepted is a political nightmare.  Operationalizing such requirements will be expensive and a nightmare at such a massive scale.  The bureaucracy and costs will add tremendous friction to the market, pushing out many companies and products. There is no doubt IoT needs significantly more security, but recommending overly broad regulations is very premature and likely damaging to everyone that benefits from smart devices. There are many other options and solutions that could deliver much better protection at a lower cost and not catastrophically impede innovation, competitiveness, and healthy market cycles. Establishing standards, best practices, for design and validation is a great start. Driving the consumers, to recognize and value secure designs, creates a competitive advantage for manufacturers to challenge each other. Open bug bounties, public security research, and sharing of penetration testing certifications would drive better processes for the IoT industry. If such practices fail to be adopted or are not sufficient, then we should discuss regulation. But first, we must pursue more optimized avenues to establish safety and security in partnership with the IoT industry, so the ecosystem can become more adaptable to evolving threats, support innovation, and be trustworthy for the benefit of all users. Let us not rush to a model of inflexible regulations, as they should only be considered as the last option. [post_title] => We Don’t Want IoT Cybersecurity Regulations [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => we-dont-want-iot-cybersecurity-regulations [to_ping] => [pinged] => [post_modified] => 2020-10-15 13:26:25 [post_modified_gmt] => 2020-10-15 20:26:25 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291708 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 3 [filter] => raw ) [6] => WP_Post Object ( [ID] => 291852 [post_author] => 11830 [post_date] => 2020-10-13 10:00:57 [post_date_gmt] => 2020-10-13 17:00:57 [post_content] => [caption id="attachment_291962" align="aligncenter" width="1138"]Executive roundtable speakers Executive roundtable speakers[/caption]

Virtual conferences are getting better all the time. Easy-to-navigate agendas, good production value in terms of visual presentation, professionally produced video segments and interspersed live events all contribute to the experience. Arm held their developers’ summit in the US on October 6-8, and it had all the attributes of a good virtual conference experience. One of the live events was an executive roundtable that took a look inside the cloud to see what impact Arm is having there.

First, a look at the panel:

Chris Bergey

Chris was the moderator. His organization is responsible for the proliferation of Arm-based solutions throughout the data infrastructure of today and tomorrow, from cloud computing to the network edge. Prior to joining Arm, Chris served as senior vice president of Devices Products at Western Digital Corporation. Previously, Chris was the vice president of Marketing at Luxtera, a silicon photonics startup, after spending over nine years at Broadcom.

Don MacAskillFounded in 2002 with a mission to support a rapidly growing global community of photographers, Don focused his passion, expertise, and business on serving the only shareholders he believes truly matter: the customer. Personally investing in everything from culture to code to customer support and everything in between over the past 17 years, Don successfully bootstrapped SmugMug Inc. which purchased Flickr from Yahoo in 2018, to not only profitability, but also into the world’s largest and most influential photographer-focused community.

Liz Fong JonesLiz is a developer advocate, labor and ethics organizer, and Site Reliability Engineer (SRE) with 16+ years of experience. She is an advocate at Honeycomb for the SRE and Observability communities, and previously was an SRE working on products ranging from the Google Cloud Load Balancer to Google Flights. She lives in Brooklyn with her wife Elly, metamours, and a Samoyed/Golden Retriever mix, and in San Francisco and Seattle with her other partners. She plays classical piano, leads an EVE Online alliance, and advocates for transgender rights.

Dave BrownDavid joined AWS in 2007, as a software developer based in Cape Town, working on the early development of Amazon EC2. Over the last 12 years, he has had several roles within Amazon EC2, working on shaping the service into what it is today. Prior to joining Amazon, David worked as a software developer within a financial industry startup.

The discussion began with Dave Brown responding the Chris’ question, “Why is AWS building Arm-based CPUs?” By the way, Amazon EC2 is the part of Amazon Web Services that provides elastic, scalable infrastructure, EC2 = Elastic Compute Cloud. Dave explained the whole thing started around 2012 with a rather familiar scenario. How to reduce workload on the mainstream processing system by offloading to dedicated accelerators. Dave referred to these accelerators as offload cards. This is rather common today, but I would say advanced thinking in 2012.

In 2018, based on the performance they were seeing from this approach, AWS launched the first server chip with an Arm core that could be used as instance type for AWS customers, and the Graviton was born. In 2019, Graviton2 was launched, providing a significant performance boost. Dave quoted a 40 percent better performance for Graviton2 instance types compared to other architectures across a wide range of customer applications.

Don MacAskill then weighed in on SmugMug’s experience with Arm in the cloud. It turns out photo serving was the first production use case for the AWS Graviton. Don’s perspective was actually not performance-centric, but rather economy-based. He explained that image processing workloads are often not CPU-bound. Rather they are bound by network bandwidth, memory, and storage I/O. This creates the situation where these applications typically over-pay for premium compute capacity that is actually not used. The Graviton architecture provided a much more cost-effective processing unit for these workloads that was actually quite fast as well. A perfect match.

Liz discussed her experiences with the Graviton architecture on Honeycomb, which is an observability tool that gathers telemetry data. It’s interesting to note that this system receives billions of events from cloud applications. Liz explained they began using Graviton2 about eight months ago, so a newer user. So far, it’s a win with a 20-30 percent performance improvement and a 20 percent price reduction.

The panel then discusses several other perspectives, including the effort to convert to Graviton. It’s an interesting and compelling dialogue. You can view the entire presentation, and other keynotes and panels by logging in here. If you don’t have an account, it’s easy to set one up. This is a great event to take a look inside the cloud to see what impact Arm is having there.

[post_title] => A Look Inside the Cloud at the Arm DevSummit 2020 [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => a-look-inside-the-cloud-at-the-arm-devsummit-2020 [to_ping] => [pinged] => [post_modified] => 2020-10-13 12:35:03 [post_modified_gmt] => 2020-10-13 19:35:03 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291852 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [7] => WP_Post Object ( [ID] => 291956 [post_author] => 16 [post_date] => 2020-10-13 06:00:36 [post_date_gmt] => 2020-10-13 13:00:36 [post_content] => Though hopefully not some of us all of the time. Randomization is a technique used in verification to improve coverage in testing. You develop tests you know you have to run, then you throw randomization on top of that to search around those starter tests, to explore possibilities you haven’t considered. Truly random tests are not actually very useful. Many won’t represent realistic possibilities, making you waste time and compute resource on useless verification. More useful is to constrain randomization in ways that should ensure the randomized tests you run are still meaningful. Unsurprisingly, this is known as constrained random testing, a mainstay in functional verification today. It’s a low effort way to increase coverage. Or is it? Constrained randomization fools us sometimes. Dave Rich at Mentor just released a white paper on that topic. Randomization Fools Us

Mixing Variable types

SystemVerilog is pretty easy-going about letting you mix types in expressions, a philosophy inherited I assume from C. In SV you can have even more finely specified word sizes than in C, but the same principle holds. From a few hundred feet up they’re all just values. Throw them together into a complex expression and let the compiler figure out the details. Especially in constraints, when we’re not trying to synthesize hardware, we just want to calculate. But the devil is in those details. Variables in a constraint sub-expression may need to be extended for correct evaluation. Expressions may overflow, with unexpected consequences. We’re pretty careful about this kind of thing in synthesis, perhaps less so in constraints. Dave uses an example expression A+B>>C>D to illustrate. This is already ugly in relying on implicit operator precedence, but beyond that, in his example A is 3-bit, B and D are 4-bit and C is an integer. The shift operation may truncate the value of A+B. As a result of which the comparison may not deliver what you expected. This is the first problem. An expression will evaluate the way the language reference manual says it should, possibly not the way you intended. There is no option for “do what I mean, not what I say” in the language. Rich shares other examples such as comparing signed and unsigned variables, where a signed value unintentionally overflows from a positive value to a negative value. Like most bugs, obvious when you see it, but easy to overlook when you forget one of the variables is signed.

Randomization adds more devilry

So far this about being careful with calculations in SystemVerilog. A generally good practice whether or not you’re using those expressions in constraints. However it’s one thing to carefully reason your way through each sub-expression when you can reason about values that make sense to you. Though Dave doesn’t mention this, I suspect there’s an additional level of danger when those variables are randomized. Did you really reason your way through all the possible randomized values those could take on? There’s one other concern in any kind of random generation, especially constrained random. That’s distribution. You want to avoid generated tests heavily weighted to certain variable values with little testing for other values. Constraints skew distributions; this is unavoidable. You need to be able to control that skew. Dave gives some hints on how this can be managed. Good white paper. You can read it in full HERE. [post_title] => Randomization Fools Us Some of the Time [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => randomization-fools-us-some-of-the-time [to_ping] => [pinged] => [post_modified] => 2020-10-13 12:36:36 [post_modified_gmt] => 2020-10-13 19:36:36 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291956 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [8] => WP_Post Object ( [ID] => 291530 [post_author] => 11830 [post_date] => 2020-10-12 10:00:29 [post_date_gmt] => 2020-10-12 17:00:29 [post_content] =>

Tempus Delivering Faster Timing Signoff with Optimal PPA

In July, I explored the benefits of the new Cadence Tempus™ Power Integrity Solution. In that piece, I explored some of the unique capabilities of this new tool with Brandon Bautz, senior product management group director and Hitendra Divecha, product management director in the Digital & Signoff Group at Cadence. I recently had the opportunity to speak with these two gentlemen again. This time, we explored the new 20.1 release of the Tempus Timing Signoff Solution in terms of its ability to deliver faster timing signoff with optimal PPA results. Once again, I was impressed by the information they provided, this time about how they are addressing the customers’ time-to-market constraints.

We began our discussion with a review of the design challenges and customer requirements. It’s well-known that design and modeling complexity are increasing at advanced nodes; and while the competitive marketplace demands higher performing devices (for longer battery life, faster compute, etc.) the time-to-market window for these devices continues to shrink. Hitendra presented a very concise summary of all these forces, included below. I haven’t seen such a coherent view like this before—it’s worth a look.

Evolving timing signoff requirements

In order to address time-to-market challenges, it’s clear that the following five items, in order by priority level, are the key customer requirements:

  1. Fewest iterations
  2. Optimization/the best PPA
  3. Fastest design closure
  4. Usability/ease-of-use
  5. World-class support

Hitendra and Brandon then went into several dimensions of the 20.1 Tempus release, which address these customer requirements while dealing with the myriad of challenges listed above. I’ll provide a short summary of each dimension here. It’s how Cadence delivers faster timing signoff with best-in-its-class PPA, but above all, it reduces the customers time-to-market challenges.

Integration with the Innovus Implementation System

The integration between various signoff quality engines at Cadence has served them well. With this integration, Cadence provides an ECO flow that is physically aware and embeds the power of path-based analysis inside the digital full flow. This seamless integration puts signoff-quality timing and power analysis in the hands of the place-and-route engineer.

As a result of the integration, engineers can achieve higher-quality block-level implementation and smoother signoff at the chip level. One can achieve 2X faster convergence with improved PPA. For example, Renesas presented their results using Tempus ECO at CadenceLIVE. They reported a designer time/effort reduction of 50% with a 10% power reduction as well. It’s not surprising that approximately 80% of Innovus customers are using Tempus ECO.

Machine Learning

Cadence has multiple initiatives to utilize machine learning (ML) techniques to drive runtime and power, performance and area (PPA) gains throughout its product lines. In the case of Tempus ECO, Cadence utilized an “ML outside” application in Cadence-speak to “learn” from numerous advanced-node designs. By analyzing the various design characteristics (slack, congestion, etc.), Cadence enhanced the optimization algorithms to improve runtime by 2X to 3.5X while still maintaining excellent PPA results.

SmartHub

This technology delivers a rich debugging toolbox through a GUI. Besides improving usability, it’s a key method that allows signoff quality information to be delivered to the place-and-route engineer in an easy-to-understand graphical manner.

C-MMMC

C-MMMC stands for concurrent multi-mode/multi-corner static timing analysis (STA). This technology provides a significant speedup in runtime for the analysis of multiple timing views by combining them into a single run. A case study from Inphi highlighted their use of C-MMMC with physically aware ECO to accelerate full-chip closure and signoff by 2X. Impressive.

SmartMMMC Optimization

With the number of views increasing for advanced nodes to 200 or more, it becomes necessary to compact these views to manage turnaround time. SmartMMMC automatically accelerates optimization across a large number of views with virtually no PPA penalty. Designers significantly benefit from this approach because they can more easily close timing across all views in a single optimization pass.

High-Capacity ECO

Beyond view count, there are also unique challenges associated with optimization of very large designs. High-capacity ECO enables the efficient optimization of large, full chip designs in a flat, easy-to-use flow. A CadenceLIVE case study from Marvell was discussed. Using this approach, Marvell was able to reduce runtime from 27 hours (traditional hierarchical Tempus ECO) to 5 hours (Tempus full-chip ECO). More impressive results.

Distributed Static Timing Analysis (DSTA) 

This one has been around a while but is quite critical to signing off extremely large designs that exist at advanced nodes. Think of performing STA on 300 million to 1 billion instances. Doing this on a huge single machine would be prohibitively expensive whereas distributing the problem across multiple, smaller machines is preferable.

The problem here is partitioning the design in a smart way so that the communication between parallel machines doesn’t negate all the benefits. Cadence has figured out a way to do just that. Given DSTA’s scalable nature, the technology is well-suited to cloud deployment. 

Summary

So ends another chapter in the Tempus story. I learned enough during my conversation with Brandon and Hitendra to know the story is far from over. There will be more installments. So, this is how Tempus reduces time-to-market challenges and delivers faster timing signoff with optimal PPA results. The key takeaway for me is that the Tempus integration with Innovus is the key driver and concurrent power and timing optimizations produce exceptional results. Also, SmartHub is impressive, enabling designers to quickly converge on their designs as full-chip ECO and DSTA allows faster design closure and shorter turn-around times.

You can learn more about the Cadence Tempus timing signoff solution here.

 

[post_title] => Tempus: Delivering Faster Timing Signoff with Optimal PPA [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => tempus-delivering-faster-timing-signoff-with-optimal-ppa [to_ping] => [pinged] => [post_modified] => 2020-10-13 08:04:39 [post_modified_gmt] => 2020-10-13 15:04:39 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291530 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [9] => WP_Post Object ( [ID] => 291859 [post_author] => 28 [post_date] => 2020-10-12 06:00:14 [post_date_gmt] => 2020-10-12 13:00:14 [post_content] => Truechip SemiWiki 2020 I am pleased to introduce Truechip to the SemiWiki community. Truechip is a leader in the IP Verification – Design and Verification solutions market, one of the fastest growing market segments we track. Truechip has been serving customers for more than 10​ years specialization in VIP integration, customization and SOC Verification. Founded in 2008, the Truechip corporate vision is to create world class Verification IP Solutions, to provide expert consultancy to the ASIC and SoC design market, to design ASICs and SoCs from architecture to working silicon, to be the leading provider of Semiconductor IP Solutions. To be a one-stop-shop for design and verification. Truechip is well known here in Silicon Valley for their collaborative customer support and services. Nitin Kishore is the Truechip founder and CEO. Nitin and Truechip are both semiconductor success stories worthy of telling so this is a great opportunity for SemiWiki, absolutely. Nitin started his career as a design engineer at ControlNet then spent 10 years at Freescale Semiconductor as Sr. Engineer and Design Manager. Seeing an opportunity, as natural born entrepreneurs do, Nitin founded Truechip. Truechip has more than 100 silicon proven Verification IPs for Storage, BUS/Interface, USB, Automotive, Memory, PCIe, Networking, MIPI, AMBA, Display, and Defence/Avionics. Truechip has a lot of technical content on their website including demos, articles and webinars under the Resources tab in the header. Seriously, there is a lot of IP content on www.truechip.net. On the demo page you can learn about CXL, PCIe Gen5, Gen4, Gen3, USB 4.0, Ethernet 800 G, TileLink, HBM, GDDR6, LPDDR5, DDR5, AMBA, and MIPI I3C 1.1 verification IPs among many others. There are more than a dozen technical articles and some very interesting webinar replays:
  • CXL - A PCIe based solution for interconnect
  • SD Express -The Future of SD Cards
  • Understanding JESD204C - A high-speed serial link between data converters and logic devices
  • Gen-Z, An Architectural Understanding
  • Revealing USB 3.2 - From Bootup
  • DDR-Exploring DIMMS
  • Ethernet-Unveiling the Basics
  • PCIe Gen4 - Decoding Verification
The next Truechip webinar is on October 13th and 14th: TileLink - Unveiling The Basics Who Should Attend :
  • Professionals working on development of Soc/IP/VIP level of TileLink.
  • Professionals working on verification of TileLink at Soc/IP/VIP level or any intermediate level.
  • People keen to know how TileLink is shaping a new era of interconnects.
  • Freshers in the field of VLSI industry.
Key Take Aways from Webinar:
  • TileLink Overview
  • Single bus interface TileLink Features
  • Use Cases
  • Truechip TileLink VIP Features & advantage
IP has been one of the most popular topics we have covered over the last 10 years and I expect that to continue. This is the beginning of a blog series on IP verification so stay tuned. About Truechip Truechip is a leading provider of Verification IP solutions. We also provide verification, DFT and Physical design services. We aid to accelerate IP/ SOC design thus lowering the cost and the risks associated with the development of ASIC, FPGA and SOC. A privately held company with a solid and seasoned leadership, having global footprints and coverage across North America, Europe and Asia. Truechip offers the Industry’s first 24 x 7 technical support. [post_title] => Verification IP Coverage [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => 291859 [to_ping] => [pinged] => [post_modified] => 2020-10-13 11:54:57 [post_modified_gmt] => 2020-10-13 18:54:57 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291859 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) ) [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object ( [ID] => 292174 [post_author] => 28 [post_date] => 2020-10-16 10:00:53 [post_date_gmt] => 2020-10-16 17:00:53 [post_content] => TSMC is the bellwether for not just the semiconductor industry but the worldwide economy. TSMC makes semiconductors, semiconductors are where electronics begin and electronics are the foundation of modern life, absolutely. Apple is also a key economic indicator and as we all know Apple is a strategic partner of TSMC. The Apple TSMC relationship started with the iPhone 6 and other iProducts (20nm in 2014) and continues to this day. The recently introduced iPhone 12 is based on TSMC 5nm. Next year Apple will use an enhanced version of 5nm and in 2022 it will be 3nm. TSMC raised its 2020 revenue forecast for a second time this year (10% -> 20% -> 30%) with strong demand for 5G and high-performance computing (HPC). The pandemic has resulted in a much stronger emphasis on mobile and cloud computing which should continue in Q4. IoT is also up but Automotive and DCE is down, again due largely to the pandemic. TSMC’s HPC (cloud) content will also benefit from additional AMD and Intel wafer agreements from 7nm down to 3nm over the next five years. TSMC Revenue Comparison: TSMC Revenue Analysis 2020 In my opinion AI and the cloud will be the key semiconductor drivers moving forward. Vast amounts of data is being generated by our electronic devices. The data is now moving to the cloud for harvesting and monetization. Cars are an easy example. I can assure you that Tesla will be using data from their cars to make more money than from the selling the cars. Think Google and search, Facebook and personal information, or Amazon and shopping, it is all about the data. It's interesting to note the process node breakout: 38% of revenue is from mature CMOS nodes. Those nodes were cloned by UMC, SMIC, and GLOBALFOUNDRIES so there is strong competition where designs can be moved from one fab to another with relative ease. That is not the case with FinFET based designs so TSMC’s strong market position will continue to evolve in the future. For 20nm and 10nm Apple was the only customer to hit HVM thus the shrinkage. TSMC moved 20nm fabs to 16nm and 12nm. The 10nm fabs were moved to 7nm and 6nm. Let’s call it the yield learning two-step where TSMC takes smaller process steps each year versus the much larger traditional semiconductor process steps.  For example, TSMC started EUV with a mature 7nm node then went full EUV at 5nm. Intel on the other hand is expected to go from zero EUV at 10nm to full EUV at 7nm. Notable C. C. Wei quotes from the Q3 2020 Earnings Call: "For TSMC, our technology leadership position enabled us to capture the industry megatrend of 5G and HPC. We expect to outperform the foundry revenue growth and grow by about 30% in 2020 in U.S. dollar terms." "This is pretty hard for me to answer, because I cannot release all the information I got from my customer. But let me say that, on the average, the 5G phone have about 30% to 40% more silicon content as compared with 4G." "We are complying full year with the regulations and so and we also notice that there is report saying that the TSMC got the (Huawei)  license. We are not going to comment on this unfounded speculation. And we also don't want to comment on our status right now. For the 4Q shipment to Huawei, the ban, the regulation already say that after September 17th, zero." "Certainly TSMC is working with all the customers and view them as our partners. And so we don't using this opportunity to raise our 8" wafer price." "We are engaging with more customer at N3 as compared with the N5 and N7 at the similar stage. So there's a lot of customers are working with us. And now, which one in the second half of 2022, which one would be the first product? Actually in smartphone and HPC applications, both." Bottom Line: TSMC and the rest of the semiconductor ecosystem seems to be somewhat COVID resistant. The new "work and learn from home" life style is accelerating the digital transformation and that means more semiconductors now and in the future. About TSMC TSMC pioneered the pure-play foundry business model when it was founded in 1987, and has been the world’s largest dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world. TSMC deployed 272 distinct process technologies, and manufactured 10,761 products for 499 customers in 2019 by providing broadest range of advanced, specialty and advanced packaging technology services. TSMC is the first foundry to provide 5-nanometer production capabilities, the most advanced semiconductor process technology available in the world. The Company is headquartered in Hsinchu, Taiwan. For more information please visit https://www.tsmc.com.   [post_title] => TSMC Sets the Stage for a Great 2021! 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TSMC Sets the Stage for a Great 2021!

TSMC Sets the Stage for a Great 2021!
by Daniel Nenni on 10-16-2020 at 10:00 am

TSMC Revenue Analysis 2020

TSMC is the bellwether for not just the semiconductor industry but the worldwide economy. TSMC makes semiconductors, semiconductors are where electronics begin and electronics are the foundation of modern life, absolutely.

Apple is also a key economic indicator and as we all know Apple is a strategic partner of TSMC. The Apple… Read More


CEO Interview: Paul Wells of sureCore

CEO Interview: Paul Wells of sureCore
by Daniel Nenni on 10-16-2020 at 6:00 am

Paul Wells SemiWiki 1

What brought you to semiconductors? 
As a kid I was interested in electronics and early personal computers. I went on to graduate from Manchester University in 1986, the birthplace of the modern computer, studying Computer Engineering where for my final year project I designed a gate array using Ferranti Electronics technology… Read More


ASML is Strong Because TSMC is Hot!

ASML is Strong Because TSMC is Hot!
by Robert Maire on 10-15-2020 at 10:00 am

TSMC ASML EUV 2020
  • ASML has strong quarter lead by great Taiwan and EUV
  • EUV “crossed over” DUV as revenue leader- signaling new era
  • Taiwan doubles, China grows, Korea weaker, US further behind

ASML hits great numbers
ASML reported revenues of Euro 4B, with income of Euro 2.54EPS, both beating estimates handily. Ten EUV systems were … Read More


Power in Test at RTL Defacto Shows the Way

Power in Test at RTL Defacto Shows the Way
by Bernard Murphy on 10-15-2020 at 6:00 am

scan chains crossing power domainspng

In the early days of Atrenta I met with Ralph Marlett, a distinguished test expert with many years of experience at Zuken and Recal Redac. He talked me into believing we could do meaningful static analysis for DFT-friendliness at RTL. His work with us really opened my eyes to the challenges that test groups face in integrating their… Read More


Concurrency and Collaboration – Keeping a Dispersed Design Team in Sync with NetApp

Concurrency and Collaboration – Keeping a Dispersed Design Team in Sync with NetApp
by Mike Gianfagna on 10-14-2020 at 10:00 am

Concurrency and Collaboration – Keeping a Dispersed Design Team in Synch with NetApp

 

In a recent post, I discussed how NetApp provides comprehensive support for moving your EDA flow to the cloud. In that post, I explored the tools, technologies and services that help design organizations move to the cloud in a coherent, predictable, and incremental manner. Having a smooth-running hybrid/on-premise or… Read More


We Don’t Want IoT Cybersecurity Regulations

We Don’t Want IoT Cybersecurity Regulations
by Matthew Rosenquist on 10-14-2020 at 6:00 am

We Dont Want IoT Cybersecurity Regulations

It simply makes no sense to call for IoT devices to be certified safe-and-secure. Before you get bent out of shape, hear me out.

Regulations are unwieldy blunt instruments, best left as a last resort. Cybersecurity regulations are not nimble, tend to be outdated the day they are instituted, and become a lowest-common-threshold… Read More


A Look Inside the Cloud at the Arm DevSummit 2020

A Look Inside the Cloud at the Arm DevSummit 2020
by Mike Gianfagna on 10-13-2020 at 10:00 am

Executive roundtable speakers

Virtual conferences are getting better all the time. Easy-to-navigate agendas, good production value in terms of visual presentation, professionally produced video segments and interspersed live events all contribute to the experience. Arm held their developers’ summit in the US on October 6-8, and it had all the attributes… Read More


Randomization Fools Us Some of the Time

Randomization Fools Us Some of the Time
by Bernard Murphy on 10-13-2020 at 6:00 am

random min

Though hopefully not some of us all of the time. Randomization is a technique used in verification to improve coverage in testing. You develop tests you know you have to run, then you throw randomization on top of that to search around those starter tests, to explore possibilities you haven’t considered. Truly random tests are not… Read More


Tempus: Delivering Faster Timing Signoff with Optimal PPA

Tempus: Delivering Faster Timing Signoff with Optimal PPA
by Mike Gianfagna on 10-12-2020 at 10:00 am

Tempus Delivering Faster Timing Signoff with Optimal PPA

In July, I explored the benefits of the new Cadence Tempus™ Power Integrity Solution. In that piece, I explored some of the unique capabilities of this new tool with Brandon Bautz, senior product management group director and Hitendra Divecha, product management director in the Digital & Signoff Group at Cadence. I recently… Read More


Verification IP Coverage

Verification IP Coverage
by Daniel Nenni on 10-12-2020 at 6:00 am

Truechip SemiWiki 2020

I am pleased to introduce Truechip to the SemiWiki community. Truechip is a leader in the IP Verification – Design and Verification solutions market, one of the fastest growing market segments we track. Truechip has been serving customers for more than 10​ years specialization in VIP integration, customization and SOC Verification.… Read More