Instrumenting Post-Silicon Validation. Innovation in VerificationInstrumenting post-silicon validation is not a new idea…Read More
Ansys Multiphysics PlatformBackground Traditionally, the interface between chip designers and…Read More
WEBINAR: Architecture Exploration of System-on-chip using VisualSim Hybrid RISC-V and ARM Processor library80% of specification optimization and almost 100% of…Read More
In every chip, power is a progressive problem to be solved. Designers have long had to rely on a combination of experience and knowledge to tackle this dilemma, typically having to wait until after silicon availability to perform power analysis with realistic software workloads. However, this is too late in the game, as it becomes… Read More
Instrumenting post-silicon validation is not a new idea but here’s a twist. Using (pre-silicon) emulation to choose debug observation structures to instrument in-silicon. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO) and I continue our series on research… Read More
A decade ago, many of us heard commentaries on how entrepreneurs were turned down by venture capitalists for not including a cloud strategy in their business plan, no matter what the core business was. Humorous punchlines such as, “It’s cloudy without any clouds” and “Add some cloud to your strategy and your future will be bright… Read More
Intel presented yesterday on their plans for process technology and packaging over the next several years. This was the most detailed roadmap Intel has ever laid out. In this write up I will analyze Intel’s process announcement and how they match up with their competitors.
10nm Super Fin (SF)
10nm is now in volume production in three… Read More
Background
Traditionally, the interface between chip designers and system power, packaging, reliability, and mechanical engineering teams was a relatively straightforward exchange of specifications. Chip designers developed preliminary power dissipation estimates, often based on a simplifying power/mm**2 value. … Read More
80% of specification optimization and almost 100% of the performance/power trade-offs can be achieved during architecture exploration of product design. RISC-V offers a huge opportunity with lots of pipeline and instruction set enhancement opportunities. Can it really attain the utopian success that people are looking… Read More
Midway through her seventh year running General Motors it’s time to assess the legacy of CEO and Chairperson Mary Barra, the first woman to run an automobile company. Of the 14 CEOs that have led GM, Barra’s term in office has been exceeded by only four of her predecessors: Alfred Sloan Jr. (May 10, 1923 – June 3, 1946), Roger
– Strong demand across logic/memory & leading/trailing edge
– Customers want units fast-no time to test
– The main question is can ASML ramp to meet demand?
Revenue & Earnings low due to systems being rushed to customers
ASML reported Euro 4B in sales and Euro 1B in net income which while within guidance… Read More
Dan is joined by Tony Pialis. Tony co-founded Alphawave in 2017 and has since served as its President and Chief Executive Officer. The journey of Alphawave is discussed, including differentiation, strategy and the IPO as well as a look to the future.
Tony co-founded Alphawave in 2017 and has since served as its President and Chief… Read More
Architectural exploration is a vast area of engineering design. It starts with the planning phase where the designer will have the list of requirements from the customer and the rough architecture most likely on a paper. Next is to assemble the model and conduct variety of trade-offs for optimization and functional studies to … Read More
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Mobileye’s Uncut Gem