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APR Tool Gets a Speed Boost and Uses Less RAM

APR Tool Gets a Speed Boost and Uses Less RAM
by Daniel Payne on 10-18-2021 at 10:00 am

Aprisa

Automatic Place and Route (APR) tools have been around since the 1980s for IC design teams to use, and before that routing was done manually by very patient layout designers. Initially the big IDMs had their own internal CAD groups coding APR tools in house, but eventually the commercial EDA market picked up this automation area,… Read More


IEDM 2021 – Back to in Person

IEDM 2021 – Back to in Person
by Scotten Jones on 10-18-2021 at 6:00 am

IEDM 2021 SemiWIki

Anyone who has read my previous articles about IEDM knows I consider it the premier conference on process technology.

Last year due to COVID IEDM was virtual and although virtual offers some advantages the hallway conversations that can be such an important part of the conference are lost. This year IEDM is returning as a live event… Read More


Silicon Startups, Arm Yourself and Catalyze Your Success…. Spotlight: Semiconductor Conferences

Silicon Startups, Arm Yourself and Catalyze Your Success…. Spotlight: Semiconductor Conferences
by Kalar Rajendiran on 10-17-2021 at 10:00 am

Live Panel

The arrival of fall seems to typically raise the number of conferences hosted by semiconductor ecosystem companies. The conferences may go by different names. But whether called a forum, summit, conference, or by some other creative name, the purpose is the same. It is to bring together technologists and business people together… Read More


Chiplet: Are You Ready For Next Semiconductor Revolution?

Chiplet: Are You Ready For Next Semiconductor Revolution?
by Eric Esteve on 10-17-2021 at 6:00 am

D2D IP market forercast 2020 2025

During the 2010-decade, the benefits of Moore’s law began to fall apart. Moore’s law stated transistor density doubled every two years, the cost of compute would shrink by a corresponding 50%. The change in Moore’s law is due to increased in design complexity the evolution of transistor structure from planar devices, to Finfets.… Read More


Podcast EP43: Navigating the Architecture Exploration Jargons and What Do They Mean to a Chip Architect?

Podcast EP43: Navigating the Architecture Exploration Jargons and What Do They Mean to a Chip Architect?
by Daniel Nenni on 10-15-2021 at 10:00 am

Dan is joined by Deepak Shankar, founder of Mirabilis Design. Dan explores the application and impact of architectural exploration on chip and system design.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group… Read More


CEO Interview: Rick Seger of SigmaSense

CEO Interview: Rick Seger of SigmaSense
by Daniel Nenni on 10-15-2021 at 6:00 am

RickSeger Photo

Rick Seger is a pioneer of the PCAP touch and pen industry. Seger formerly was the President of N-trig, which incorporated PCAP technology with active pen solutions into devices for nearly all major PC OEMs. Microsoft acquired N-trig in 2015, and Seger is now the CEO of SigmaSense, a global leader in touch sensing performance. SigmaSense… Read More


Webinar – Comparing ARM and RISC-V Cores

Webinar – Comparing ARM and RISC-V Cores
by Daniel Payne on 10-14-2021 at 10:00 am

Mirabilis Webinar, October 21

Operating systems and Instruction Set Architectures (ISA) can have long lifespans, and I’ve been an engineering user of many ISAs since the 1970s. For mobile devices I’ve followed the rise to popularity of the ARM architecture, and then more recently the RISC-V ISA which has successfully made the leap from university… Read More


SeaScape: EDA Platform for a Distributed Future

SeaScape: EDA Platform for a Distributed Future
by Daniel Nenni on 10-14-2021 at 6:00 am

EDA Platform for a Distributed Future

The electronic design community is well aware that it faces a daunting challenge to analyze and sign off the next generation of huge multi-die 3D-IC systems. Most of today’s EDA tools require extraordinary resources in specialized computers with terabytes of RAM and hundreds of processors. Customers don’t want to keep buying… Read More


Webinar – SoC Planning for a Modern, Component-Based Approach

Webinar – SoC Planning for a Modern, Component-Based Approach
by Mike Gianfagna on 10-13-2021 at 10:00 am

Webinar – SoC Planning for a Modern Component Based Approach

We all know that project planning and tracking are critical for any complex undertaking, especially a complex SoC design project. We also know that IP management is critical for these same kinds of projects – there is lots of IP from many sources being integrated in any SoC these days. If you don’t keep track of what you’re using and… Read More


TSMC Arizona Fab Cost Revisited

TSMC Arizona Fab Cost Revisited
by Scotten Jones on 10-13-2021 at 8:00 am

TSMC North America Fabs

Back in May of 2020 I published some comparisons of the cost to run a TSMC fab in Arizona versus their fabs in Taiwan. I found the fab operating cost based on the country-to-country difference to only be 3.4% higher in the US and then I found an additional 3.8% because of the smaller fab scale. Since that time, I have continued to encounter… Read More