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Multiple Monopole Exposures: The Correct Way to Tame Aberrations in EUV Lithography?

Multiple Monopole Exposures: The Correct Way to Tame Aberrations in EUV Lithography?
by Fred Chen on 02-01-2023 at 6:00 am

Multiple Monopole Exposures 1

For a leading-edge lithography technology, EUV (extreme ultraviolet) lithography is still plagued by some fundamental issues. While stochastically occurring defects probably have been the most often discussed, other issues, such as image shifts and fading [1-5], are an intrinsic part of using reflective EUV optics. However,… Read More


Lam chops guidance, outlook, headcount- an ugly, long downturn- memory plunges

Lam chops guidance, outlook, headcount- an ugly, long downturn- memory plunges
by Robert Maire on 01-31-2023 at 2:00 pm

Lamb chops

-Lam Research chops guidance, outlook & headcount sharply
-Further declines as 2023 will be H1 weighted- No end in sight
-System sales cut by more than half as even service is cut
-Memory is the culprit as expected-Forcing business “reset”

A sad sounding conference call….

While Lam reported a good December,… Read More


Weebit ReRAM: NVM that’s better for the planet

Weebit ReRAM: NVM that’s better for the planet
by Eran Briman on 01-31-2023 at 10:00 am

1.Weebit Nano RRAM ReRAM IP NVM for semiconductors green materials Eco friendly technology production

Together with our R&D partner CEA-Leti, we recently completed an environmental initiative in which we analyzed the environmental impact of Weebit’s Resistive Random-Access Memory (ReRAM / RRAM) technology compared to Magnetoresistive Random Access Memory (MRAM) – another emerging non-volatile memory (NVM) technology.… Read More


Model-Based Design Courses for Students

Model-Based Design Courses for Students
by Bernard Murphy on 01-31-2023 at 6:00 am

System design min

Amid the tumult of SoC design advances and accompanying verification and implementation demands, it can be easy to forget that all this activity is preceded by architecture design. At the architecture stage the usual SoC verification infrastructure is far too cumbersome for quick turnaround modeling. Such platforms also tend… Read More


Counter-Measures for Voltage Side-Channel Attacks

Counter-Measures for Voltage Side-Channel Attacks
by Daniel Payne on 01-30-2023 at 2:00 pm

agileGLITCH min

Nearly every week I read in the popular press another story of a major company being hacked: Twitter, Slack, LastPass, GitHub, Uber, Medibank, Microsoft, American Airlines. What is less reported, yet still important are hardware-oriented hacking attempts at the board-level to target a specific chip, using voltage Side-Channel… Read More


Achronix on Platform Selection for AI at the Edge

Achronix on Platform Selection for AI at the Edge
by Bernard Murphy on 01-30-2023 at 10:00 am

Edge compute

Colin Alexander ( Director of product marketing at Achronix) released a webinar recently on this topic. At only 20 minutes the webinar is an easy watch and a useful update on data traffic and implementation options. Downloads are still dominated by video (over 50% for Facebook) which now depends heavily on caching at or close to … Read More


Taming Physical Closure Below 16nm

Taming Physical Closure Below 16nm
by Bernard Murphy on 01-30-2023 at 6:00 am

NoC floorplan

Atiq Raza, well known in the semiconductor industry, has observed that “there will be no simple chips below 16nm”. By which he meant that only complex and therefore high value SoCs justify the costs of deep submicron design.  Getting to closure on PPA goals is getting harder for such designs, especially now at 7nm and 5nm. Place and… Read More


Podcast EP141: The Role of Synopsys High-Speed SerDes for Future Ethernet Applications

Podcast EP141: The Role of Synopsys High-Speed SerDes for Future Ethernet Applications
by Daniel Nenni on 01-27-2023 at 10:00 am

Dan is joined by Priyank Shukla, Staff Product Manager for the Synopsys High Speed SerDes IP portfolio. He has broad experience in analog, mixed-signal design with strong focus on high performance compute, mobile and automotive SoCs and he has a US patent on low power RTC design.

Dan explores the use of high-speed SerDes with Priyank.… Read More


CTO Interview: John R. Cary of Tech-X Corporation

CTO Interview: John R. Cary of Tech-X Corporation
by Daniel Nenni on 01-27-2023 at 6:00 am

20220307SpanishHillsTacoDinner blurred 1

John R. Cary is professor of physics at the University of Colorado at Boulder and CTO of Tech-X Corporation. He received his PhD from the University of California, Berkeley, in Plasma Physics.  Prof. Cary worked at Los Alamos National Laboratory and the Institute for Fusion Studies at the University of Texas, Austin, prior to joining… Read More


ASML – Powering through weakness – Almost untouchable – Lead times exceed downturn

ASML – Powering through weakness – Almost untouchable – Lead times exceed downturn
by Robert Maire on 01-26-2023 at 10:00 am

Robert Maire Bloomberg

-Demand far exceeds supply & much longer than any downturn
-Full speed ahead-$40B in solid backlog provides great comfort
-ASP increase shows strength- China is non issue
-In a completely different league than other equipment makers

Reports a good beat & Guide

Revenues were Euro6.4B with system sales making up Euro4.7B… Read More