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Podcast EP100: A Look Back and a Look Ahead with Dan and Mike

Podcast EP100: A Look Back and a Look Ahead with Dan and Mike
by Daniel Nenni on 08-12-2022 at 10:00 am

Dan and Mike get together to reflect on the past and the future in this 100th Semiconductor Insiders podcast episode. The chip shortage, foundry landscape, Moore’s law, CHIPS Act and industry revenue trends are some of the topics discussed.

The views, thoughts, and opinions expressed in these podcasts belong solely to … Read More


CEO Interview: Kai Beckmann, Member of the Executive Board at Merck KGaA

CEO Interview: Kai Beckmann, Member of the Executive Board at Merck KGaA
by Daniel Nenni on 08-12-2022 at 6:00 am

Kai Beckmann 1

Kai Beckmann is a Member of the Executive Board at Merck KGaA, Darmstadt, Germany, and the CEO of Electronics. He is responsible for the Electronics business sector, which he has been leading since September 2017. In October 2018, Kai Beckmann also took over the responsibility for the Darmstadt site and In-house Consulting. In… Read More


Understanding Sheath Behavior Key to Plasma Etch

Understanding Sheath Behavior Key to Plasma Etch
by Scott Kruger on 08-11-2022 at 10:00 am

Final Edit EtchingProcess Illustration

Readers of SemiWiki will be well aware of the challenges the industry has faced in photolithography in moving to new nodes, which drove the development of new EUV light sources as well as new masking techniques.  Plasma etching is another key step in chip manufacturing that has also seen new challenges in the development of new sub-10nm… Read More


WEBINAR: Design and Verify State-of-the-Art RFICs using Synopsys / Ansys Custom Design Flow

WEBINAR: Design and Verify State-of-the-Art RFICs using Synopsys / Ansys Custom Design Flow
by Synopsys on 08-11-2022 at 8:00 am

Synopsys Ansys RF Flow Webinar

The design and characterization of RF circuits is a complex process that requires an RF designer to overcome a variety of challenges. Not only do they face the complexities posed by advanced semiconductor processes and the need to meet the demanding requirements of modern wireless standards, designers must also account for electromagnetic… Read More


Flex Logix Partners With Intrinsic ID To Secure eFPGA Platform

Flex Logix Partners With Intrinsic ID To Secure eFPGA Platform
by Kalar Rajendiran on 08-11-2022 at 6:00 am

SoC Block Diagram with EFLX and QuiddiKey

While the ASIC market has always had its advantages over alternate solutions, it has faced boom and bust cycles typically driven by high NRE development costs and time to market lead times. During the same time, the FPGA market has been consistently bringing out more and more advanced products with each new generation. With very… Read More


Podcast EP99: How Cliosoft became the leading design data management company

Podcast EP99: How Cliosoft became the leading design data management company
by Daniel Nenni on 08-10-2022 at 10:00 am

Dan is joined by Srinath Anantharaman, who founded Cliosoft in 1997 and serves as the company’s CEO. He has over 40 years of software engineering and management experience in the EDA industry.

Dan and Srinath explore the original focus for Cliosoft and how that has expanded over the years. The future of Cliosoft, as well as its plans… Read More


Coverage Analysis in Questa Visualizer

Coverage Analysis in Questa Visualizer
by Bernard Murphy on 08-10-2022 at 6:00 am

Questa coverage

Coverage analysis is how you answer the question “have I tested enough?” You need some way to quantify the completeness of our testing; coverage is how you do that. Right out of the gate this is a bit deceptive. To truly cover a design our tests would need to cover every accessible state and state transition. The complexity of that task… Read More


Intel and TSMC do not Slow 3nm Expansion

Intel and TSMC do not Slow 3nm Expansion
by Daniel Nenni on 08-09-2022 at 10:00 am

Pat Gelsinger and CC Wei SemiWiki

The media has gone wild over a false report that Intel and TSMC are slowing down 3nm. It is all about sensationalism and getting clicks no matter what damage is done to the hardworking semiconductor people, companies and industry as a whole. And like lemmings jumping off a cliff, other less reputable media outlets perpetuated this… Read More


Fast EM/IR Analysis, a new EDA Category

Fast EM/IR Analysis, a new EDA Category
by Daniel Payne on 08-09-2022 at 6:00 am

IR Drop min

I’ve watched the SPICE market segment into multiple approaches, like: Classic SPICE, Parallel SPICE, FastSPICE and Analog FastSPICE. In a similar fashion the same thing just happened to EM/IR analysis, because after years of waiting we finally have a different approach to EM/IR analysis that works at the top-level of … Read More


EUV’s Pupil Fill and Resist Limitations at 3nm

EUV’s Pupil Fill and Resist Limitations at 3nm
by Fred Chen on 08-08-2022 at 10:00 am

EUV Pupil Fill and Resist Limitations at 3nm p1

The 3nm node is projected to feature around a 22 nm metal pitch [1,2]. This poses some new challenges for the use of EUV lithography. Some challenges are different for the 0.33NA vs. 0.55NA systems.

0.33 NA

For 0.33 NA systems, 22 nm pitch can only be supported by illumination filling 4% of the pupil, well below the 20% lower limit for

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