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[post_content] => 
Welcome to my weekly roundup of the key semiconductor news from around the world from last week. The COVID-19 virus outbreak and it’s impact on the semiconductor supply chain continues to dominate the news, but there was also lots of other news from around the world, so please read on.
Let's start by a review of where the started at the end of January. This article from SEMI shows that through December into January there was a steady recovery in the global electronic supply chain, with both the SEMI equipment market showing growth and the global purchasing managers index moving into expansion territory in January. But in late January COVID-19 began to make its negative impact felt, causing disruption to supply chains and shutting down factories around Wuhan, China and other electronics manufacturing centers. The full impact of the COVID-19 outbreak has yet to show in the numbers and will only be seen in February and March sales numbers.
The impact of COVID-19 on the various semiconductor manufacturing segments is analysed in these 2 articles, one from ECNS in China and one from EETimes. They both paint the same picture reporting the wafer Fab sector doesn’t seem to be badly affected with most Fabs up and running. This maybe partly due to the locations of the wafer fabs and also partly due to the level of automation used in manufacturing in the wafer sector. The main impact is being seen downstream in assembly plants and other components manufacturing sites for optics and sensors where due to the labour intensive nature of the manufacturing and also the fact that a lot of these factories closed over Chinese New Year and so were not allowed to restart until Feb 10th or even later, and some are still pending approval from local governments to restart. Also even when they can restart, getting back the full workforce is still a big challenge with many people still quarantined, so for assembly and optical/sensor suppliers there is some impact, but this will only really be felt in the coming weeks. Another sector impacting the supply chain is logistics of shipping product. Despite the overall disruption the sentiment is that the sector will recover once the outbreak s over.
This week Apple issued a rare revenue warning that the March quarter would be lower than previous guidance due to the impact of COVID-19, however Apple did not give a revised guidance. There is also expected to be an impact to other Chinese phone companies like Huawei, Oppo and Xiaomi who mainly produce in China as well as suppliers like Foxconn.
Samsung has also been affected by COVID-19 as this weekend they announced that one coronavirus case had been confirmed at its mobile device factory complex in the southeastern city of Gumi, Korea, causing a shutdown of its entire facility there until Monday morning. The plant produces only a small proportion of Samsung’s phone with most production being done in Vietnam and India.
Away from COVID-19, Dialogue announced it will acquire Adesto for $500 million enterprise value ($12.55 per share in cash),. Adesto was founded in 2006 and based in Santa Clara, is a leading provider of innovative custom integrated circuits (ICs) and embedded systems for the Industrial Internet of Things (IIoT) market, Adesto has approximately 270 employees.
The US continues in it’s plans to impose more restrictions on companies selling technology to Huawei. This week the Pentagon dropped it’s opposition to the US Commerce Dept’s proposal to further tighten restrictions on selling American technology to Huawei, by tightening the rule from 20% to 10% content.
At the same time as law makers were planning to put in extra restrictions, the Commerce department announced that Huawei will get another 45 day reprieve from the original restriction by granting another temporary general license. This is the 4th extension to date, previously 3 90 day temporary general licences have been issued in May, Aug & Nov.
In addition Huawei has said it has secured more than 90 commercial 5G contracts worldwide, an increase of nearly 30 from last year despite the relentless pressure from U.S. authorities. In a press conference in London on Tuesday, Ryan Ding, president of Huawei's carrier business group said "We have 91 commercial 5G contracts worldwide, including 47 from Europe," and added that "One year ago, I said we are leading by 18 months ahead of our competitors in 5G technology. Now, we still maintain that leadership."
Compound semiconductor substrate manufacturer, AXT, said that it’s Q4 revenue dropped 17% yoy due to a drop in GaAs and Ge substrate sales. For full-year 2019, reported revenue of $83.3m, down 18.7% compared to 2018.
Market research company Yole Développement expects the global 3D imaging and sensing market to expand from $5.0 billion in 2019 to $15.0 billion in 2025, at a 20 percent CAGR. They expect the 3D sensing main trend to switch from the front to the rear of phones with the adoption of ToF camera's mass adoption. According to Yole's 3D imaging & sensing report, rear attachment will surpass front attachment with market penetration rate reaching about 42 percent in 2025.
STMicroelectronics has announced a collaboration with TSMC to accelerate the development of Gallium Nitride (GaN) process technology and the supply of both discrete and integrated GaN devices to market. Through this partnership, ST’s GaN products will be manufactured using TSMC’s GaN process technology.
Finally a couple of articles about the semiconductor supply chain. One article from SEMI is about building a healthy supply chain for critical subsystem components where the lack of alternative suppliers causes significant risks.
Another article is by UCLA Anderson where they reviewed pricing in the semiconductor industry and found that in about 26% of transactions rather than getting volume discounts the manufacturer charged more for large quantities, and this shows how the supplier values production capacity when negotiating pricing.
That’s all for this week, if you enjoyed what you read, please do help to like and share my article so that others may also enjoy it.
[post_title] => The COVID-19 Virus Outbreak and the Semiconductor Supply Chain
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Cryptocurrency fraud is aggressively on the rise and topped over $4 billion last year, according to the security tracking company Chainalysis.
This is especially shocking to those who thought they had found an incredible investment in the cryptocurrency world, yet were swindled out of everything. As part of these cryptocurrency scams, victims are lured into investing with the hype of significant returns. Once committed, they are often shown how their accounts are quickly accruing vast wealth, which encourages them to pour even more of their money into the con. The mirage eventually disappears, as does the money, when the operation shutters without notice and the swindlers vanish will all the deposits. Victims are left with the realization they were duped as part of an elaborate hoax and powerless to recover their money.
Chainalysis recently produced an industry report highlighting the scope of the problem. The organization specializes in helping businesses and governments understand illegal cryptocurrency transactions. The data showcases the rapid rise in 2019 of big Ponzi scams that represented the bulk of the losses. The top six of the large-scale scams were collectively responsible for about 90% of the fraud. It proves when cybercriminals find the right lure in the cryptocurrency community, such as a Ponzi style scam, the momentum quickly accelerates and draws more into the system, becoming massive in scale.
Fraudsters like cryptocurrency
Some of the beneficial attributes of cryptocurrency are being leveraged against those who aren’t mindful of the risks. Cryptocurrency has a reputation for a financial opportunity because of its history of volatile price swings, both high and low. Media has spotlighted many who have made considerable fortunes with meager beginnings. Scammers take advantage and reach out to this growing global community that desires fast riches, yet is very naïve with the risks.
The ability to transfer crypto tokens virtually, means they are everywhere but nowhere. Criminals understand this dichotomy and use it to their advantage. Once the money is in the hands of crooks, it begins a rapid journey across the digital landscape and into dark corners where it is hard to trace or impound.
Victims are often left with a total loss and little hope they will ever get any of their money back. For criminals, the potential of unimaginable gains, sometimes in the hundreds of millions of dollars or more, far exceeds the risk of being caught and prosecuted.
Privacy, Regulations, and Law Enforcement on the edge
Part of what makes these scams so attractive for cybercriminals to run is the ability to remain unidentified. The inherent anonymity of users is a challenge in the cryptocurrency world. Regulatory rules for Know Your Customer (KYC) and Anti-Money Laundering (AMC) are proliferating across legitimate exchanges and services, which greatly help identify fraudsters and increase accountability, but there is a lack of consistency and there are always workarounds. Other services promote their support for customer privacy and account anonymity, often finding loopholes or outright avoiding such requirements.
Many of these services are not intentionally malicious or fraudulent, but as part of their belief in the benefits of privacy, they are indirectly supporting potentially illicit activities. Overall, the vast majority of cryptocurrency transactions are legitimate and only a small minority of the overall transactions are tied to illegal activity. But criminals will use whatever tools available to shield themselves from accountability and prosecution.
Many in the crypto community, who are doing nothing illegal, greatly value their privacy and anonymity. They are attracted to services that don’t require identification and keep their transactions confidential. There is a natural tension in the system that the growing community is still struggling with. I have spoken with many who are staunch advocates for their rights of privacy, in some cases even to the extent of being un-trackable by governments, yet show immediate regret and anger at those same entities when they lose money to a fraudster and have no recourse for justice. Still, some accept those risks as table stakes and prefer to remain anonymous.
Law enforcement is facing great difficulties adapting to digital crimes but is slowly getting better. For cryptocurrency, they work with experts to track transactions in public blockchains and collaborate with major exchanges to identify criminal activities and trace the flow of illicit funds. It is not easy and the growing number of victims makes it impossible to help even a fraction of those defrauded. The focus tends to be on big cases, like the multi-billion-dollar PlusToken Ponzi scam in 2019 where millions of users were told they could earn 10% a month on their investment. Ultimately, the criminals pulled in over $2 billion before it collapsed and the money is now gone. It has been digitally laundered and dispersed among thousands of anonymous accounts.
Although Chinese authorities were able to identify and apprehend 6 of the individuals behind the scheme, most crimes go unsolved. The chance of restitution for the PlusToken victims is almost non-existent.
The continued rise of the cryptocurrency market and ease in which to convince victims encourages the greed of fraudsters. Scams are getting more elaborate and convincing. Law enforcement is getting better but must face the evolving challenges of technology. More ‘privacy’ designed currencies are gaining momentum and will pose new hurdles to investigate and prosecute criminals, forcing authorities to continually adapt. In the meanwhile, people will be at risk. So far, using common sense in vetting investments is the best way to avoid cryptocurrency victimization.
[post_title] => Cryptocurrency Fraud Reached $4.3 Billion in 2019
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[post_content] => Ron Lowman, product marketing manager at Synopsys, recentl
y posted an interesting technical bulletin on the Synopsys website entitled How AI in Edge Computing Drives 5G and the IoT. There’s been a lot of discussion recently about the emerging processing hierarchy of edge devices (think cell phone or self-driving car), cloud computing (think Google, Amazon or Microsoft) and the newest middle ground in between (edge computing). The current deployment of 5G networks delivers the capability of creating much more data than ever before, and how and where that data will be processed makes the processing hierarchy even more important.
Some facts are in order. First an observation from me – please don’t think 5G is for your cell phone. While your carrier will likely make a big deal about 5G reception, that isn’t the primary use of this technology; your cell phone is plenty fast enough now. 5G holds the promise of wirelessly linking many other data sources in a high bandwidth, low latency way. This is part of the promise of IoT. A quote from Ron’s piece helps drive home the point:
“By 2020, more than 50 billion smart devices will be connected worldwide. These devices will generate zettabytes (ZB) of data annually growing to more than 150 ZB by 2025.” (Data courtesy of Cisco.)
A little perspective is in order. A zettabyte is a billion terabytes, or 1,000,000,000,000,000,000,000 bytes if you prefer the long form. According to Wikipedia, in 2012 there was upwards of 1 zettabyte of data in existence in the world. So, a 150-fold increase, just from edge devices, is kind of daunting. Given this situation, when you consider the traditional model of IoT (edge device) data processing in the cloud, a few problems come up. Ron’s article provides this catalog of issues:
- 150ZB of data will create capacity issues if all processed in a small number of places
- Transmitting that much data from its location of origin to centralized data centers is quite costly, in terms of energy, bandwidth, and compute power
- Power consumption of storing, transmitting and analyzing data is enormous
Regarding the second point, Ron goes on to report that estimates project only 12% of current data is even analyzed by the companies that own it and only 3% of that data contributes to any meaningful outcomes. So, finding an effective way to reduce cost and waste is clearly needed. Edge computing holds great promise to deal with these issues by decentralizing the processing task – essentially bringing it closer to the data source. More benefits reported by Ron include:
- Enable network reliability as applications can continue to function during widespread network outages
- Potential security improvements by eliminating some threat profiles such as global data center denial of service (DoS) attacks
- Provide low latency for real-time use cases such as virtual reality arcades and mobile device video caching
The last point is quite important. Ron points out that “cutting latency will generate new services, enabling devices to provide many innovative applications in autonomous vehicles, gaming platforms, or challenging, fast-paced manufacturing environments.” While local processing can go a long way to reduce waste and cost, more efficient methods are also important. Ron points to AI as a critical enabler for this to happen.
With this backdrop, Ron explores various edge computing use cases, market segments and the impact all this will have on server system SoCs. One use case described by Ron centers on the Microsoft HoloLens. It’s a fascinating case study of augmented reality and its demands for low latency and low power. Ron then talks about the power, processing and latency requirements of the various edge computing segments. If you think there’s one edge computing scenario, think again. The piece concludes with a discussion of the impact all this will have on server system SoCs. AI accelerators are a key piece of this discussion.
If any of this gets your attention, I strongly recommend reading Ron’s complete technical bulletin. There is a lot of compelling detail there regarding AI and the edge. For the chip designers out there, I’ll leave you with one excerpt from Ron’s piece that summarizes the challenges and opportunities of the next generation of edge computing.
[post_title] => Edge Computing – The Critical Middle Ground
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[post_content] => 
As a professional conference attendee I look for the most meaningful way to spend my time and workshops is one of the best. Especially when a customer is involved and there is no bigger EDA customer than Intel, absolutely.
System Level Flows for SoC Architecture Analysis and Design
Speakers:
Swaminathan Ramachandran - CircuitSutra Technologies Pvt. Ltd.
Umesh Sisodia - CircuitSutra Technologies Pvt. Ltd.
Prassana Sadananda Rao - Intel Corp.
Organizer:
Umesh Sisodia - CircuitSutra Technologies Pvt. Ltd.
This workshop covers the latest trends and best practices in the domain of ESL methodologies for SoC Architecture, Co-Design, Co-Verification & raising the abstraction of chip design through High Level Synthesis. These advanced flows are enabled by using C, C++, SystemC, TLM2.0 along with traditional RTL flows.
Talk 1: Defining a SystemC Methodology for your Company
Swaminathan Ramachandran, CircuitSutra Technologies
As SystemC gains popularity in the fields of architecture evaluation, virtual platform development, SoC level verification, etc., more teams and companies want to explore, experiment and deploy it for their modeling use cases. While SystemC library provides the vocabulary and the nuts and bolts to build a useful and diverse set of models, it is sometimes too low level to be immediately useful. What is needed is a SystemC library analogous to Boost libraries in C++, for building blocks like memories, buses, registers, timers, etc. along with the infrastructure to quickly stitch them together into a working platform asap. Most of the Semiconductor companies who have successfully deployed SystemC, have developed their own tool independent methodology on top of SystemC, and they use it together with advanced modeling tools from EDA vendors. Such a library usually starts with basic building blocks, and over a period of time becomes a very rich collection of re-usable modeling components that can be re-used across various IP models, SoC variants, Modeling Use cases, business units, etc.
Any company looking to adopt SystemC in their flows should carefully conceptualize the development of such a methodology inhouse and can learn from the best practices being followed in the Industry. In this presentation, we will talk about what should be the content of such a methodology/library and how it should be conceptualized.
CircuitSutra has worked with leading semiconductor companies for more than a decade now and has participated in modeling projects from the stage of experimentation to pilot projects and to widespread adoption. We have an in-depth understanding of the best practices followed in the modeling domain.
Talk 2: System Flows in a “hybrid” Environment – Intel's Approach
Prassana Sadananda Rao - Intel Corp.
The validation of SOCs at System level with full FW/SW stack in the pre-silicon stage itself is essential to accelerate SW readiness, improve RTL quality and overall shorten the product development cycle.
SoC FPGAs and Virtual Platforms (VP) are amongst the standard de-fact pre-Si solutions, However, each comes with its pro and cons: SoC FPGA has RTL accuracy but is available only after SoC integration is completed. VP arrives early but is more of an architectural model rather than RTL instantiation. To address this problem, our work describes an alternative leading-edge solution that starts at IP level itself. Single IP FPGA integrated into Virtual Platform (i.e., Hybrid IP-FPGA). Such a solution has the advantage of being available as soon as VP is ready. At the same time, it provides the IP RTL design with the necessary system-level context (i.e., interaction with FW/SW/Drivers of other components) which allows an early validation of IP design in an integrated environment instead of in isolation/standalone mode.
As a case study, we would present the results achieved on a complex PCI IP responsible for audio and sensing processing being integrated into one of the latest Intel SoC platforms. The IP was mapped to an IP FPGA, the SoC is modeled as a loosely timed Virtual Prototype and a hybrid layer plays the role of the glue logic for the two technologies. The overall Hybrid IP FPGA solution is proven to have a production level maturity that allowed the validation of complex system-level flows, such as security handshakes and power state transitions (reboot, S3, S4, and S5). Our case-study utilized only production-level SW/FW (the same that will be used on the real silicon) and enabled a tight interaction between the FPGA and other IPs of the platform thus exercising system-level flows which would be only visible when silicon is in the lab. This work set the foundation for making VP as the backbone of standalone IP RTL integration and candidates the proposed methodology as a breakthrough player in the pre-Si validation strategy of new SoC programs.
We will also discuss the challenges we faced while developing such a new methodology. In particular, the extra requirements that the VP model must satisfy to seamlessly integrate the hardware of the FPGA. As an example, the logic associated with the low-level hardware signals crossing the cutline of the two technologies must be modeled on VP with RTL accuracy in order to cope with FPGA expectations. Our future focus will be on developing VP interfaces in a scalable way to productize and scale such hybrid technology over a large set of different IPs.
Talk 3: Using High-Level Synthesis to Migrate Software Algorithms to Semiconductor Chip Designs
Umesh Sisodia, CircuitSutra Technologies
High-Level Synthesis (HLS) raises the abstraction of chip design beyond RTL. It enables the implementation of design functionality in high-level languages like C++/SystemC, and generates corresponding RTL using HLS tools. Synthesizable C++/SystemC code for design is very concise as compared to equivalent RTL code for the same design. Moreover, simulation of C++/SystemC models is much faster compared to RTL simulation. This allows significant productivity gains in the design and verification process. HLS also allows separation of functionality from architecture constraints and technology parameters, thus permitting code re-use across different variants of semiconductor chips, or across FPGA and ASICs.
HLS flows are more effective for algorithm centric designs. Nowadays we see new chip design requirements for emerging domains like 5G, Deep Learning, Vision, Image Processing, Speech, Audio processing etc. In these domains, there are many algorithms implemented in software, and several of these are available as open source.
In this talk, we will present an HLS based methodology to quickly migrate a software algorithm implemented in plain C/C++ to a hardware implementation in RTL for semiconductor chips (FPGA or ASIC). We will also cover a verification flow that allows the reuse of the original test suite of the software algorithm to verify the synthesizable C++/SystemC model as well as the final RTL. The untimed C++/SystemC models are also suitable to be used in Virtual Platforms, that allows embedded software development much before the chip is designed.
This methodology accelerates the pace of innovation, enables faster rollout of new chips, permits experimentation by quickly trying out the functionality in software and hardware, and taking high-level architecture decisions much earlier in the cycle.
Talk 4: SystemC Methodology for RISC-V Ecosystem
Umesh Sisodia, CircuitSutra Technologies
SystemC is a C++ library created for design and verification at the SoC and system level. It is widely used in the industry for system-level modeling, virtual prototyping, hardware-software co-verification, architecture & performance modeling, high-level synthesis, and functional verification.
RISC-V is an open-source processor ISA. Given that RISC-V ecosystem is in a nascent stage, yet there is widespread interest in the industry to explore the usage of RISC-V for various use cases. A robust modeling eco-system is necessary for the successful adoption of a new ISA, and in this context, a need exists for SystemC modeling infrastructure for RISC-V ecosystem. In this presentation, we will talk about some essential components required for anyone trying to deploy SystemC based methodologies for their RISC-V project.
CircuitSutra is an Electronics System Level (ESL) design IP and services company, headquartered in India, having development centers in Noida and Bangalore, and serves the customers worldwide. It enables customers to adopt advanced methodologies based on C, C++, SystemC, TLM, IP-XACT, UVM-SystemC, SystemC-AMS, Verilog-AMS. Its core competencies include Virtual Prototype (Development, Verification, Deployment), Architecture & Performance modeling, Co-simulation, Co-emulation, HLS, SoC & System verification.
[post_title] => System Level Flows for SoC Architecture Analysis and Design - DVCON 2020
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[post_content] => PowerMOS devices play a major role in a variety of power converter and control circuits. Some examples of their applications include PMICs, or boost and buck converters. Often these are used in mobile and IoT devices to convert battery voltages to circuit operating voltages.
Due to their size and internal complexity PowerMOS devices have to be analyzed as hundreds or perhaps thousands of smaller devices, connected by a complex web of metallization. The first and most significant effect of this is non-uniform switching, with gate voltage varying across the device during device turn on. This in turn leads to Ids concentrating in some areas and not others.
Transient electrical analysis is capable of showing detailed gate voltages and current densities during the transitions, when devices typically experience their highest power draw. However, there is a second dimension to the problem that influences the electrical analysis – intrinsic device behavior is temperature dependent. As a result, device current values will rise as temperature rises, and the reciprocal is true, temperature will rise as more current flows. In the worst case, this vicious cycle may lead to temperature related device failure if the metal melts and shorts out the junction.
The thermal dynamics depend of the properties of the die, the surrounding package and even the board. Uncoupled electrical and thermal analysis will have difficulty converging on an accurate solution at each time step during circuit operation.
Analysis tools are needed to thoroughly model the internal behavior of these complex devices during their operation. Magwel’s PTM-ET tool combines joule heating in the metal interconnect and device junctions with other heat sources and sinks to determine device thermal behavior during circuit activity. PTM-ET concurrently simulates the interdependence between electrical behavior and thermal behavior. PTM-ET’s unique concurrent and dynamic simulation of devices in their packaging with user provided stimulus provides an accurate picture of circuit operation over time.
With the information from PTM-ET, designers can make sure that the optimal packaging has been selected, keeping costs down and also ensuring device reliability. Another advantage of electro-thermal co-simulation is that it can help identify hot spots in the device and guide the placement of sense or replica devices.
Magwel is offering a free webinar on March 10th at 10AM PST covering the topic of concurrent electro-thermal analysis for PowerMOS devices with the goal of understanding impacts on device operation. The talk by Allan Laser, Magwel Field Application Engineer, will discuss the challenges of modeling device behavior and predicting the effects of thermal and electrical factors. Magwel’s PTM® tools work off of device layout and foundry supplied intrinsic device models and produce a comprehensive look at PowerMOS devices.
[post_title] => Webinar on Concurrent Electro-Thermal Analysis for PowerMOS Devices to Improve Performance and Reliability
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[post_content] => At the recent DesignCon 2020 in Santa Clara, Cadence introduced a new product, Sigrity Aurora. You won’t find a press release about this announcement. Rather, Brad Griffin, product management group director at Cadence, presented Sigrity Aurora in the theater at the Cadence booth. This one caught my eye and deserves some discussion. DesignCon has become a system-oriented event. Think chip, package, PC board and chassis. This breadth of problem-solving has created a large and very diverse show floor and technical program. Relevant, real-world system design challenges are treated here. If you missed it, I highly recommend catching DesignCon next year.
Sigrity Aurora is a product that addresses the signal and power integrity (SI/PI)
challenges associated with high-performance PCB design. The question posed by Brad in his presentation was quite simple – how many times do you iterate between design and analysis in a PC board design? That is, iteration between the PCB designer and SI/PI engineer? I can tell you from first-hand experience this kind of back-and-forth can waste a lot of time. If you’re not careful, you tie up a very valuable and scarce resource, the SI/PI expert.
The disparate expertise of a PCB designer and an SI/PI engineer contribute to the challenges here. So does a disparate tool flow with lots of conversions and mapping. In his theater presentation, Brad posed a way to address all these issues. What if you had a single vendor solution that could address: schematics, re-route signal and power integrity (SI/PI) analysis, placement, routing, in-design SI/PI analysis and final signoff?
It turns out Cadence has the product breadth to offer such a solution, and that was the essence of the announcement. Thanks to their Sigrity product line, Cadence has an extensive set of analysis engines to address tasks such as screening technology (impedance and coupling checks), return path checking, SI analysis (reflection and crosstalk) and PI analysis (IR drop).
And thanks to the new Sigrity Topology Explorer, pre-route and signal net extraction can be one to support what-if analysis.
The punchline of Brad’s presentation was that all of this capability can now be delivered through the popular Cadence Allegro PCB editing and routing technologies with Sigrity Aurora, which can read and write directly to the Allegro PCB database. A powerful set of analysis engines with a tight and efficient integration to a familiar implementation flow. The applications of such a tool are diverse and significant. A few scenarios were illustrated in Brad’s presentation as follows.
Screening technology for electrical rules checks (no models required)
Impedance analysis screening:
- Same requirements on stack-up
- Global view of results more accessible
- Look for outliers
Coupling analysis screening:
- No SI model required
- Electrical coupling is more accurate than geometrical methods
- Global view of results
Return path screening:
- Report nets with possible return path problems
- Use a figure of merit such as return path quality factor
- Return path visualization
Signal integrity technology (driven by industry-standard IBIS models)
Reflection analysis output:
Crosstalk analysis output:
Power integrity technology (driven by Allegro PowerTree technology)
IR drop analysis output (IR drop vision can be displayed as voltage, IR drop, or current density):
And pulling it all together, system-level simulation for signoff
If you’re engaged in high-performance PCB design, this comprehensive design flow is definitely worth a look.
[post_title] => Bridging the Gap Between Design and Analysis
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A funny thing happened on the way to Barcelona for the annual Mobile World Congress (MWC) event scheduled for this week. The event organizer - the GSMA – exhibitors and attendees were forced to come to terms with the risk of contracting and spreading the coronavirus – COVID 19.
Several large European, South Korean, and U.S. telecommunications and technology companies made the earliest choice not to attend the event, while Chinese telecommunications and technology suppliers cautioned against hysteria. In the midst of a global technology trade war and the onset of 5G network technology promising massive commercial opportunities for upgrading network gear and handsets, LG and Ericsson were the first two companies to opt out of MWC.
Ericsson rival Nokia announced its own exit from the event days later and a cascade of cancellations followed. But it seemed that Chinese suppliers of equipment, with the exception of early exiter ZTE, were among the most hesitant to cancel – certainly not the first.
The slow decision of Huawei to cancel its participation in MWC, in particular, is an ominous coda to the termination of the 2020 event. Of all technology companies in the world, Huawei ought to have been the first to cancel, particularly considering the company has operations in Wuhan, in Hubei province at the epicenter of the epidemic – the impact of which is still unfolding.
Even after dozens of companies had opted out of MWC in the interest of the health and well-being of their employees and the public in general, Huawei appeared to stay the course. The company noted its own internal measures to quarantine employees and limit travel for those already affected by the virus. But, surely, the announced MWC departures of arch rivals Ericsson and Nokia might have served notice to senior management that it was time to shut down attendance plans.
Unique among all MWC attendees, Huawei was making its decisions while under a political spotlight facing allegations of being a threat to national security from the U.S. In fact, the U.S. continued to raise these concerns in the past week with European partners during the Munich Conference – a point of contention with European allies less obsessed with potential security threats posed by Huawei.
But Huawei’s behavior during the MWC cancellation brouhaha was telling. Crass commercial interests were clearly prioritized over the safety of Huawei employees or fellow MWC exhibitors or show attendees. It is enough to bring to mind the spate of employee suicides at Foxconn – attributed to unbearable working conditions.
By its decision not to cancel its MWC participation Huawei sent a clear signal to the entire telecommunications and technology industry that commercial interests were paramount. The European Union may be standing by Huawei in the face of U.S. pressure to limit implementation of Huawei 5G equipment on the continent, but Huawei’s lack of concern over the potential spread of COVID 19 – death toll now approaching 2,000 – is a clear warning sign for all and a failure of Huawei’s management.
[post_title] => Huawei Sends Unmistakable Message
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[post_content] => Custom AI acceleration continues to gather steam. In the cloud, Alibaba has launched its own custom accelerator, following Amazon and Google. Facebook is in the game too and Microsoft has a significant stake in Graphcore. Intel/Mobileye have a strong lock on edge AI in cars and wireless infrastructure builders are adding AI capabilities to small cells and base stations for 5G. All of these applications depend on a lot of flexibility and future-proofing for long-term relevance in rapidly evolving environments.
But there are many applications, probably accounting for the great majority of units, for which power, cost or transparent use models are much more important metrics. An agricultural monitor in a field in the middle of nowhere, a microwave voice controller, traffic sensors distributed across a large city. For these a general-purpose solution, even a general-purpose AI solution, may be overkill. An application-specific AI function would be much more compelling.
Pre-AI times, you would immediately think of a hardware accelerator – some function that would do whatever it had to do but much faster than running a software equivalent on the CPU. That’s pretty much what an AI accelerator does. It may still be software driven but not in the same way as a general-purpose CPU. Software is developed in Python on a big platform such as TensorFlow or Torch then compiled through multiple steps onto the target accelerator.
Therein lies the magic. That accelerator can be as wild as you want it to be as long as it stays within the general bounds of a neural net architecture. It may support multiple convolution engines, each in turn supported by SRAM for the accelerator as a whole, along with local memories to optimize access for a preferred ordering of operations.
It may support specialized functions for common operations such as pooling. For speed and power, it will commonly support different word widths at different stages of inference and specialized optimizations in handling sparse arrays. These are both hot areas of innovation in neural net architectures, some architects even experimenting with single-bit weights – if a weight can only be 1 or 0, you don’t need multiplication in convolution and sparseness increases!
The challenge in all of this is that you have so many knobs you can turn that it becomes difficult to know where to start or if you have really explored the full space of possibilities when you want to commit to a final architecture. Compounding the problem, you need to test and characterize over a large range of large test-cases – big images, speech samples and so on.
Running the majority of your testing in C rather than RTL is just common sense since it will run orders of magnitude faster and it’s easier to tune than the RTL. Also, neural net algorithms map well through high-level synthesis (HLS), so your C model can be more than a model – it can be the implementation from which you generate the RTL. You can explore the power, performance and area implications of choices you are considering - multiple convolution processors, local memories, word widths, broadcast updates. All with a fast turn-around time, allowing you to more fully explore the range of possible optimizations.
Mentor has just released a white paper with a nice intro on some of the architectural tradeoffs in building such accelerators. You can register to get the paper HERE.
[post_title] => High-Level Synthesis at the Edge
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[post_content] => KLA saw its share of the semiconductor metrology/inspection market increase from 52% in 2018 to 56% in 2019.
As a background, KLA manufactures and sells equipment used to monitor many of the 400 to 600 processing steps in the manufacturing of semiconductors, starting with a bare wafer, such as silicon, to a completed device. The company makes metrology systems used to measure parameters such as thin film thickness or linewidths, and inspection systems used to detect defects and monitor abnormalities in production.
Except for a small percentage of sales of non-metrology/inspection equipment that came with the acquisition of Orbotech, KLA generates nearly 80% of revenue from metrology/inspection.
According to The Information Network’s report entitled “Metrology, Inspection, and Process Control in VLSI Manufacturing" KLA was the only company among competitors to demonstrate positive growth in 2019. This report analyzes 17 different segments of the overall sector, and there are individual leaders in each of the segments. KLA, of course, with a dominant market share, leads many of the segments.
As shown in the chart below, KLA grew 2% in revenues in 2019. It’s closest competitor, Applied Materials had revenue growth of -10.1% in 2019.
ASML, the dominant lithography market leader, is the leader in the electron beam inspection segment, yet its share of the overall decreased year-on-year 23.3% in 2019.
Nanometrics and Rudolph Technology announced that their merger was finalized in 4Q 2019, (new company named Onto Innovation), but I kept them separated in this chart. Rudolph Technology’s revenue dropped 18.3% YoY and Nanometric’s revenue dropped 16.7% YoY in the metrology/inspection sector.
In the overall metrology/inspection market, KLA increased its share from 52% in 2018 to 56% in 2019. Hitachi High Technologies’ share of the market in 2019 decreased from 10.4% in 2018 to 9.1%. Next was Applied Materials market share decreased from 10.1% to 9.1%.
[post_title] => KLA Blows Away Competition in the Semiconductor Metrology/Inspection Market
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[post_content] => I recently spent some time at DesignCon 2020 in Santa Clara. For those who haven’t attended this show in a while, you need to go. It’s no longer a small event focused on chip design. It has grown into a true system-level conference, with a broad ecosystem represented on the show floor and in the technical sessions. Ecosystem is an important concept regarding DesignCon. Many of the technical papers present a collaboration between two or more companies to achieve a particular system design goal.
The first presentation I attended at the show fit this model quite well, with Cadence Design Systems and Marvell Semiconductor presenting a joint modeling and optimization project. The session started at 8:00 AM and the room was almost full – a good indicator of interest in the topic.
Let’s start by unpacking the title of the presentation. IBIS (I/O Buffer Information Specification) is a standard to describe IC input/output analog characteristics. The Algorithmic Modeling Interface (AMI) added the ability to describe the signal processing (algorithmic) portions of channel in a standard way, along with the analog portion. The goals of this work target the development of models that are interoperable, portable, flexible, high-performance, accurate and secure. The addition of a back-channel interface (BCI) specification allows simulation of channels that employ link training, which involves optimizing transmitter characteristics based on receiver observations, sent as messages over the channel.
The presentation included remarks from Steven Parker (senior staff engineer at Marvell) and Jared James (principal product engineer at Cadence). Their remarks focused on modeling a 56G PAM4 SerDes that was designed by the GLOBALFOUNDRIES team prior to their acquisition by Marvell. Methods to achieve interoperability between different tools using the IBIS-AMI standard were discussed, along with an overview of using the BCI to implement simulations of back-channel optimization. The figure below shows the process flow to implement back-channel training.
From a big picture point of view, the figure below illustrates the predicted improvements in channel performance based on the use of link training.
Results (with and without BCI)
Cadence developed a SerDes model for its Sigrity SystemSI technology using IEEE constructs. The Marvell model was built using internal tools. Marvell then modified its model to conform to the constructs used by Cadence and a system simulation was then built using the Cadence tools for transmit and the Marvell tools for receive. An excellent example of the cross-platform compatibility offered by IBIS-AMI. Some of the lessons learned from this work include:
- The need for a command acknowledge function to determine the specific command that caused limits of calibration for the receiver to be reached
- Consistent command sequence numbering to ensure commands remain in order
- Setting the timing of commands correctly – too little time and the transmitter may not be able to react, too much and there will be dead time, extending simulation runs
And some comments on potential interoperability improvements:
- Protocol compatibility improvement: develop de-facto standards to support popular training schemes
- Open source an API for available models that describes the interface to the model and its files
- A more general specification from IBIS to handle a broader range of applications
The work presented has been used successfully on several projects. Inter-vendor interoperability can be achieved with proper planning and coordination. This work has broad application going forward, including support for the emerging chiplet market.
[post_title] => IBIS-AMI Back-Channel System Optimization in Practice
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[post_content] => Welcome to my weekly roundup of the key semiconductor news from around the world from last week. The COVID-19 virus outbreak and it’s impact on the semiconductor supply chain continues to dominate the news, but there was also lots of other news from around the world, so please read on.
Let's start by a review of where the started at the end of January. This article from SEMI shows that through December into January there was a steady recovery in the global electronic supply chain, with both the SEMI equipment market showing growth and the global purchasing managers index moving into expansion territory in January. But in late January COVID-19 began to make its negative impact felt, causing disruption to supply chains and shutting down factories around Wuhan, China and other electronics manufacturing centers. The full impact of the COVID-19 outbreak has yet to show in the numbers and will only be seen in February and March sales numbers.
The impact of COVID-19 on the various semiconductor manufacturing segments is analysed in these 2 articles, one from ECNS in China and one from EETimes. They both paint the same picture reporting the wafer Fab sector doesn’t seem to be badly affected with most Fabs up and running. This maybe partly due to the locations of the wafer fabs and also partly due to the level of automation used in manufacturing in the wafer sector. The main impact is being seen downstream in assembly plants and other components manufacturing sites for optics and sensors where due to the labour intensive nature of the manufacturing and also the fact that a lot of these factories closed over Chinese New Year and so were not allowed to restart until Feb 10th or even later, and some are still pending approval from local governments to restart. Also even when they can restart, getting back the full workforce is still a big challenge with many people still quarantined, so for assembly and optical/sensor suppliers there is some impact, but this will only really be felt in the coming weeks. Another sector impacting the supply chain is logistics of shipping product. Despite the overall disruption the sentiment is that the sector will recover once the outbreak s over.
This week Apple issued a rare revenue warning that the March quarter would be lower than previous guidance due to the impact of COVID-19, however Apple did not give a revised guidance. There is also expected to be an impact to other Chinese phone companies like Huawei, Oppo and Xiaomi who mainly produce in China as well as suppliers like Foxconn.
Samsung has also been affected by COVID-19 as this weekend they announced that one coronavirus case had been confirmed at its mobile device factory complex in the southeastern city of Gumi, Korea, causing a shutdown of its entire facility there until Monday morning. The plant produces only a small proportion of Samsung’s phone with most production being done in Vietnam and India.
Away from COVID-19, Dialogue announced it will acquire Adesto for $500 million enterprise value ($12.55 per share in cash),. Adesto was founded in 2006 and based in Santa Clara, is a leading provider of innovative custom integrated circuits (ICs) and embedded systems for the Industrial Internet of Things (IIoT) market, Adesto has approximately 270 employees.
The US continues in it’s plans to impose more restrictions on companies selling technology to Huawei. This week the Pentagon dropped it’s opposition to the US Commerce Dept’s proposal to further tighten restrictions on selling American technology to Huawei, by tightening the rule from 20% to 10% content.
At the same time as law makers were planning to put in extra restrictions, the Commerce department announced that Huawei will get another 45 day reprieve from the original restriction by granting another temporary general license. This is the 4th extension to date, previously 3 90 day temporary general licences have been issued in May, Aug & Nov.
In addition Huawei has said it has secured more than 90 commercial 5G contracts worldwide, an increase of nearly 30 from last year despite the relentless pressure from U.S. authorities. In a press conference in London on Tuesday, Ryan Ding, president of Huawei's carrier business group said "We have 91 commercial 5G contracts worldwide, including 47 from Europe," and added that "One year ago, I said we are leading by 18 months ahead of our competitors in 5G technology. Now, we still maintain that leadership."
Compound semiconductor substrate manufacturer, AXT, said that it’s Q4 revenue dropped 17% yoy due to a drop in GaAs and Ge substrate sales. For full-year 2019, reported revenue of $83.3m, down 18.7% compared to 2018.
Market research company Yole Développement expects the global 3D imaging and sensing market to expand from $5.0 billion in 2019 to $15.0 billion in 2025, at a 20 percent CAGR. They expect the 3D sensing main trend to switch from the front to the rear of phones with the adoption of ToF camera's mass adoption. According to Yole's 3D imaging & sensing report, rear attachment will surpass front attachment with market penetration rate reaching about 42 percent in 2025.
STMicroelectronics has announced a collaboration with TSMC to accelerate the development of Gallium Nitride (GaN) process technology and the supply of both discrete and integrated GaN devices to market. Through this partnership, ST’s GaN products will be manufactured using TSMC’s GaN process technology.
Finally a couple of articles about the semiconductor supply chain. One article from SEMI is about building a healthy supply chain for critical subsystem components where the lack of alternative suppliers causes significant risks.
Another article is by UCLA Anderson where they reviewed pricing in the semiconductor industry and found that in about 26% of transactions rather than getting volume discounts the manufacturer charged more for large quantities, and this shows how the supplier values production capacity when negotiating pricing.
That’s all for this week, if you enjoyed what you read, please do help to like and share my article so that others may also enjoy it.
[post_title] => The COVID-19 Virus Outbreak and the Semiconductor Supply Chain
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Welcome to my weekly roundup of the key semiconductor news from around the world from last week. The COVID-19 virus outbreak and it’s impact on the semiconductor supply chain continues to dominate the news, but there was also lots of other news from around the world, so please read on.
Let’s start by a review of where the started… Read More
Cryptocurrency fraud is aggressively on the rise and topped over $4 billion last year, according to the security tracking company Chainalysis.
This is especially shocking to those who thought they had found an incredible investment in the cryptocurrency world, yet were swindled out of everything. As part of these cryptocurrency… Read More
Ron Lowman, product marketing manager at Synopsys, recently posted an interesting technical bulletin on the Synopsys website entitled How AI in Edge Computing Drives 5G and the IoT. There’s been a lot of discussion recently about the emerging processing hierarchy of edge devices (think cell phone or self-driving car), cloud… Read More
As a professional conference attendee I look for the most meaningful way to spend my time and workshops is one of the best. Especially when a customer is involved and there is no bigger EDA customer than Intel, absolutely.
System Level Flows for SoC Architecture Analysis and Design
Speakers:
Swaminathan Ramachandran – … Read More
PowerMOS devices play a major role in a variety of power converter and control circuits. Some examples of their applications include PMICs, or boost and buck converters. Often these are used in mobile and IoT devices to convert battery voltages to circuit operating voltages.
Due to their size and internal complexity PowerMOS … Read More
At the recent DesignCon 2020 in Santa Clara, Cadence introduced a new product, Sigrity Aurora. You won’t find a press release about this announcement. Rather, Brad Griffin, product management group director at Cadence, presented Sigrity Aurora in the theater at the Cadence booth. This one caught my eye and deserves some discussion.… Read More
A funny thing happened on the way to Barcelona for the annual Mobile World Congress (MWC) event scheduled for this week. The event organizer – the GSMA – exhibitors and attendees were forced to come to terms with the risk of contracting and spreading the coronavirus – COVID 19.
Several large European, South Korean, and U.S.
…
Read More
Custom AI acceleration continues to gather steam. In the cloud, Alibaba has launched its own custom accelerator, following Amazon and Google. Facebook is in the game too and Microsoft has a significant stake in Graphcore. Intel/Mobileye have a strong lock on edge AI in cars and wireless infrastructure builders are adding AI capabilities… Read More
KLA saw its share of the semiconductor metrology/inspection market increase from 52% in 2018 to 56% in 2019.
As a background, KLA manufactures and sells equipment used to monitor many of the 400 to 600 processing steps in the manufacturing of semiconductors, starting with a bare wafer, such as silicon, to a completed device. The… Read More
I recently spent some time at DesignCon 2020 in Santa Clara. For those who haven’t attended this show in a while, you need to go. It’s no longer a small event focused on chip design. It has grown into a true system-level conference, with a broad ecosystem represented on the show floor and in the technical sessions. Ecosystem is an important… Read More
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Hybrid Verification for Deep Sequential Convergence