SIC 2020 Forum 800x100

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Powering the Next Generation of Hearables and Wearables with ChipusChipus is an interesting company. It’s been around since 2008 and focuses on mixed-signal ASICs, intellectual property blocks and IC design services. They are headquartered on the island of Florianopolis, which is described as the most dense startup ecosystem in Brazil. The company has substantial skills in analog and mixed signal designs, but they’ve also successfully delivered designs in FinFET technologies from RTL to tapeout. Having spent time in analog, mixed signal and FinFET design, I can tell you it’s a rare blend of skills to be able to address all of these disciplines. You can learn more about Chipus from the interview Dan Nenni did with their CEO, Murilo Pilon Pessatti here. Recently, I had an opportunity to preview a webinar that discusses powering the next generation of hearables and wearables with Chipus. IoT is hot, so this one certainly caught my attention.

[caption id="attachment_293062" align="alignright" width="106"]Murilo Pessatti Murilo Pessatti[/caption]

The webinar is presented by Murilo Pessatti, CEO of Chipus and Heider Marconi, manager of technical sales at Chipus. Murilo co-founded Chipus. He started working with semiconductor design more than 15 years ago. Between 2003 and 2005, he worked in the power management group of Chipidea Microelectronics, Portugal (acquired by Synopsys). After his experience in Europe, Murilo joined CEITEC (a Brazilian IDM Company) as technical leader and project manager for three years. He holds an MSEE degree in analog IC design from UNICAMP (State University of Campinas) and also has background in project management.

[caption id="attachment_293063" align="alignright" width="105"]Heider Marconi Heider Marconi[/caption]

Heider was previously CEO of DFchip, a design house and IP provider focused on developing efficient and low power circuits. He joined Chipus three years ago. Both these gentlemen have substantial background in power management and this was the focus of the webinar.

The webinar began with an overview of the hearables and wearables market and Chipus from Murilo. While these kinds of devices have been around for a long time, they are now becoming quite ubiquitous and consumers are demanding smaller, lighter and more comfortable devices. Success in this market will be decided by fashion trends and the devices themselves must accommodate those trends.

Applications include entertainment, health monitoring and augmented reality. Murilo shared some market size data, which is absolutely staggering.  You’ll need to watch the webinar to see the numbers for yourself. Murilo also discussed some work Chipus is doing with GLOBALFOUNDRIES on their 22nm FD-SOI technology, called 22FDX. After a discussion of market dynamics, Murilo handed the presentation over to Heider, who presented a comprehensive power management IP solution from Chipus based on GF 22FDX.

This IP handles a great deal of the power management functions for IoT class devices, including battery charging and battery management as well as overall power management for the chip. Since every design is different, the IP is highly configurable, allowing substantial power management offloading from the main processing portion of the design. Heider goes into a lot of detail, you really need to see the webinar and check it out.

The webinar concludes with a robust Q&A, addressing some very relevant application-level questions. The webinar replay is available HERE. I was amazed at the size of this segment of the IoT market. It’s definitely worth the time to see how Chipus is powering the next generation of hearables and wearables.

About Chipus

Chipus Microelectronics (ISO 9001:2015 certified) is a semiconductor company focused on the development of mixed-signal ASICs, intellectual property (IP) blocks and IC design services.

The company has more than 200 analog IP blocks in process nodes from 22nm to 0.35um of various foundries. Since its foundation in 2008, Chipus has worked with customers worldwide (South and North America, Europe, and Asia) with firm commitment and flexible client support.

Besides analog and mixed-signal expertise, Chipus also offers custom digital IC design services having successfully delivered designs in FINFET technologies from RTL to backend.

Headquartered in Florianópolis, Brazil, Chipus has a US subsidiary in Silicon Valley and sales teams in both USA and Europe.
 
 
 
 
 
 
 
 

[post_title] => Powering the Next Generation of Hearables and Wearables with Chipus [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => powering-the-next-generation-of-hearables-and-wearables-with-chipus [to_ping] => [pinged] => [post_modified] => 2020-11-24 11:27:10 [post_modified_gmt] => 2020-11-24 19:27:10 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=293033 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [1] => WP_Post Object ( [ID] => 292891 [post_author] => 28 [post_date] => 2020-11-16 06:00:30 [post_date_gmt] => 2020-11-16 14:00:30 [post_content] => The Cadence Virtuoso Design System has been one of the premier Integrated Circuit design systems for many years and is used by most major semiconductor companies.  While it is powerful and versatile, it is often not optimized for certain complex, repetitive and time-consuming layout design tasks. Header Webinar 1 skillcad The founder and president of SkillCAD, Pengwei Qian saw, that often layout tasks in Cadence required many mouse clicks for even simple tasks.  And as the number of clicks increased, along with increased human interaction, the possibility of design errors increased.  He felt that if both complex and tedious repetitive, layout tasks could be simplified and automated, not only would layout productivity be increased, but human errors, and costly design rework, would be greatly reduced.  “Correct and Optimized  by Construction” was the goal but without the expense of loss of control by the layout designer. Originally containing a handful of commands to help with common layout tasks, SkillCAD has evolved into over 100 functions, including the powerful, patented V-Editor tools, metal routing tools that allow the designer to route one or fifty metal lines with equal ease, pin placing tools that allow the placement of hundreds of pins in a matter of seconds, and many other tools, that greatly improve a  layout design team productivity. REGISTER HERE What you will Learn in the webinar: Whatever layout design approach is used, bottom-up, top-down, or any combination of approaches, the power and versatility of the SkillCAD tools will shorten layout cycle times.
  • The powerful pin placement and modifying tools can take the placement of hundreds of pins, from hours to a matter of a few minutes.
  • The many metal routing and bus routing tools, make routing and editing metal routes, easy and efficient by…
  • Running wide power and ground metals and creating mesh ground metal planes with the slotted metal tools, is as easy as routing a single metal wire.
  • The dummy fill and density checking tools, make generating matched dummy metals over critical circuit areas and quickly checking density percentages in circuit blocks, as easy as specifying the layers and identifying a circuit region.
In addition to these commonly used tools, SkillCAD also provides powerful tools for generating and editing guard rings around devices, circuit elements, and even entire circuit blocks.
  • There are tools for generating shielding around sensitive metal signals, and even creating the complex twisted metal structures, with shielding, that are common for sensitive RF (Radio Frequency) transmission lines.
  • SkillCAD also includes tools for measuring circuit data, comparison viewing of old versus new circuit data, viewing cross sections of MOS devices, and many other tools not mentioned here.
REGISTER HERE About SkillCAD Founded in 2007 to enhance productivity to Cadence Virtuoso layout design flow. Cadence Virtuoso + SkillCad have become the industry standard layout environment for full custom analog, RF, and mixed-signal designs. Over 80% of the major analog and mixed signal (AMS) companies use SkillCad. SkillCad seamlessly integrates with Cadence Virtuoso Layout L, XL and GXL and supports IC5, IC6, IC12, IC18. SkillCad has been a Cadence Connection Partner since 2008. [post_title] => Webinar: Increase Layout Team Productivity with SkillCAD [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => webinar-increase-layout-team-productivity-with-skillcad [to_ping] => [pinged] => [post_modified] => 2020-11-16 07:01:09 [post_modified_gmt] => 2020-11-16 15:01:09 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292891 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [2] => WP_Post Object ( [ID] => 293039 [post_author] => 28 [post_date] => 2020-11-15 10:00:43 [post_date_gmt] => 2020-11-15 18:00:43 [post_content] => Well, it’s official, the TSMC Board of Directors approved an investment to establish a wholly-owned subsidiary in Arizona with a paid-in capital of $3.5 billion. As history shows the investment may be more than that but $3.5B is a great starting point. This is being discussed in the SemiWiki Forum  and I have been gathering inside intelligence from the ecosystem so let me offer my experience, observation, and opinion. TSMC North America SemiWiki This is a GREAT political move by TSMC that will help insure the independence of Taiwan, absolutely. It’s only 20,000 wafers per month to start but it can be expanded quite rapidly as TSMC expertly does. Consider this first fab a “toe in the water” test to see how the US Government responds. In my opinion the target customers would be the US Government and suppliers. Xilinx for example does quite a bit of government business with their FPGAs. Intel is shipping 16nm products today so a US based 5nm fab in 2024 would be perfect timing for Xilinx "made in the USA" customers. And yes I know that TSMC built a fab (WaferTech) in the United States in 1996 but that was a joint partnership with three other companies. TSMC bought out the partners and now runs it as a wholly owned subsidiary. Unfortunately, this “toe in water” move is certainly not a guarantee of political success. TSMC did a similar toe in water test in China with Fab 16 in Nanjing (2016) which did not go as planned. Rumor has it the China Government took this olive branch and used it to advance the China semiconductor initiative by “monitoring” construction and recruiting TSMC employees: China hires over 100 TSMC engineers in push for chip leadership, Emerging chipmakers offer lavish pay packages to snap up talent. TSMC also has an older 200mm fab in Shanghai but competing against the China Government backed SMIC is now rather challenging for foreign owned manufacturing companies inside of China. The ultimate goal of course is for TSMC to be an active part of the H.R.7178 - CHIPS for America Act introduced in Congress on June 11th, 2020. Given the importance of semiconductors to modern life let’s hope this bill passes and ushers in a new era of global semiconductor collaboration, absolutely. Creating Helpful Incentives to Produce Semiconductors for America Act or the CHIPS for America Act This bill establishes investments and incentives to support U.S. semiconductor manufacturing, research and development, and supply chain security. Specifically, the bill provides an income tax credit for semiconductor equipment or manufacturing facility investment through 2026. The bill also establishes a trust fund to be allocated upon reaching an agreement with foreign government partners to promote (1) consistency in policies related to microelectronics, (2) transparency in microelectronic supply chains, and (3) alignment in policies towards nonmarket economies. The Department of Commerce shall, through the National Institute of Standards and Technology (NIST), carry out a program of research and development investment to accelerate the design, development, and manufacturability of next generation microelectronics, including through the creation of a Manufacturing USA institute for semiconductor manufacturing. Commerce shall also establish a program to match state and local government incentives offered to private entities for the purposes of building fabrication facilities relating to semiconductor manufacturing. Further, Commerce shall assess the capabilities of the U.S. industrial base to support the national defense in light of the global nature of supply chains and interdependencies between the industrial bases of the U.S. and foreign countries with respect to the manufacture and design of semiconductors. The Department of Defense shall prioritize the use of specified available amounts for programs, projects, and activities in connection with semiconductor and related technologies. The President shall establish within NIST a subcommittee on matters relating to U.S. leadership in semiconductor technology and innovation, which shall develop a national strategy on semiconductor research. “Semiconductors were invented in America and U.S. companies still lead the world in chip technology today, but as a result of substantial government investments from global competitors, the U.S today accounts for only 12 percent of global semiconductor manufacturing capacity,” said Keith Jackson, President, CEO, and Director of ON Semiconductor and 2020 SIA chair. “The CHIPS for America Act would help our country rise to this challenge, invest in semiconductor manufacturing and research, and remain the world leader in chip technology, which is strategically important to our economy and national security. We applaud the bipartisan group of leaders in Congress for introducing this bill and urge Congress to pass bipartisan legislation that strengthens U.S. semiconductor manufacturing and research.” [post_title] => TSMC to Build first US Fab in Arizona! [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => tsmc-to-build-first-us-fab-in-arizona [to_ping] => [pinged] => [post_modified] => 2020-11-16 06:58:41 [post_modified_gmt] => 2020-11-16 14:58:41 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=293039 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 8 [filter] => raw ) [3] => WP_Post Object ( [ID] => 292996 [post_author] => 14 [post_date] => 2020-11-15 06:00:50 [post_date_gmt] => 2020-11-15 14:00:50 [post_content] => Robert Maire Bloomberg DRAM 2020 has been a NAND growth year-2021 will be the year of DRAM. While foundry logic has gotten all the credit in 2020 the reality is that NAND has been up 2X in 2020 for semiconductor equipment provider Applied Materials (AMAT). It is expected that NAND will be flat in 2021 while DRAM will take over the growth slot with foundry/logic remaining the "steady eddie" grower.
Not much Kokusai Komment
Management did say they continue to believe that the Kokusai transaction will close by end of year but we take that with a very large grain of salt as we have seen this movie before with the Applied/TEL merger and the LAM/KLA merger. both of which dragged on before dying a slow death. As we have previously mentioned , we think one of the ways this deal could get done is as an "olive branch" from China to the new incoming administration. Given that this is just a "bolt on" acquisition with little synergy, we see little negative from the continued delay.
Applied claiming share gains versus industry
Applied spoke about year on year gains and numbers that implied outgrowing the market. When you dig into the numbers a bit more it would appear that they kept market share roughly flat in the NAND market versus the rest of the industry while taking some share in foundry/logic as that has been more of a core market for the company versus the memory market. So the reality is that its likely more of a case of who is spending rather than Applied actually taking significant business from competitors.
Service is super solid
As we have seen with most other companies in the industry, the service business has grown to become an outsize portion of the overall business as the installed base becomes huge and the tool complexity with less sophisticated customers increases. This recurring revenue stream is a great offset to the overall cyclicality of the systems business which gets better and smoother as the percentage continues to increase.
Display is OK
The display business being flat is more or less as expected. It remains a good but certainly not exciting business and perhaps not as attractive nor wildly exciting as the core semi business. There are not a lot of near term technology or capacity drivers expected that will move the needle in this space so we just view it and expect it to be a flattish performer
The Stocks- Is good good enough?
Applied was up a couple of percent in the aftermarket on the very solid results and upbeat commentary. Its hard not to like the results and financials and bullish commentary but it may not be a big enough beat to sustain upward momentum. It was good but the expectation was for it to be good after hearing from ASML, LRCX and KLAC. It also wasn't significantly better. The overall chip industry has been very good in 2020 versus the rest of the world as semiconductors have been needed for Covid alternatives and technology that continues to march on. We are perhaps more optimistic, given the election results, that the China cloud that has hung over the industry will dissipate but it may take a few quarters. The potential uptick in DRAM is certainly more promising as that spend could be a lot higher than lost SMIC spend. On a collateral basis we don't expect as much of a move from sub suppliers as they have already reported good news and the Applied news is not incrementally positive on top of that. ASML, LRCX and KLAC will likely see little additional benefit from the Applied quarter.‌ [post_title] => 2021 will be the year of DRAM! [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => 2021-will-be-the-year-of-dram [to_ping] => [pinged] => [post_modified] => 2020-11-16 07:00:08 [post_modified_gmt] => 2020-11-16 15:00:08 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292996 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 2 [filter] => raw ) [4] => WP_Post Object ( [ID] => 292786 [post_author] => 11830 [post_date] => 2020-11-13 10:00:42 [post_date_gmt] => 2020-11-13 18:00:42 [post_content] => [caption id="attachment_292921" align="alignright" width="218"]Jim Hogan Jim Hogan[/caption]

Power seems to be on everyone’s mind these days. Hyperscale data centers worry about operating costs unless power is optimized. The AI accelerators in the Edge can’t be effective without optimized power. Advanced 2.5 and 3D packages simply can’t remove the heat unless power is optimized.  And then there’s all those gadgets we carry and wear. Power optimization allows us to go a full day without plugging them in. There are plenty of other scenarios, but you get the idea. This is a big topic, with implications from chip design to system design. To get a comprehensive view on the topic, I tapped industry luminary Jim Hogan. Having worked in semis, EDA and system companies, Jim brings all perspectives to the table. I wanted to see what Jim thought about the history and significance of power optimization.

We started at the beginning. When did Jim first realize power was important to optimize? Jim explained that heat was the enemy in many early designs and that led to a focus on power optimization. All this started in the early 1990’s according to Jim. His experience is largely at Cadence, but he also gave a nod to Apache Design Solutions (now part of ANSYS), which came along a bit later and did a lot to focus and define the transistor level power optimization market. Speaking of Apache, Jim pointed out their favorable exit with ANSYS, but cautioned this is not an easy market – it took Apache over a decade to achieve that result. Good things seldom happen overnight.

Jim credits the Apache acquisition by ANSYS for creating an inflection in the market. Apache did a lot to define the market and the ANSYS acquisition created interest from the larger EDA players. It also brought ANSYS closer to the EDA market. With this backdrop, Jim began discussing power in a broader sense with Dr. Vojin Zivojnovic, AGGIOS founder and CEO. During this time, there was a lot of focus on transistor-level power optimization with other physical design and process scaling efforts.

Vojin had been brainstorming a different approach with some key technical collaborators. One that focused on software and its impact on power. Jim recalls a discussion during DAC 2010 in Anaheim, CA with Vojin. The simple observation made during that discussion was that software only consumes power when its running. What could be done to exploit that to reduce power and heat? Vojin and Jim agreed there was a significant business and technical opportunity in all this. And so AGGIOS was born.

I explored software vs. hardware power optimization with Jim. Were they two different ways to solve the same problem, and if so, which was better? Jim felt the two approaches were different and came at the problem with a different set of goals that would yield a different set of results. From a historical perspective, there was an important change in system design philosophy that began around 2005. Up to that point, processor architectures were defined to serve a market and the specs for those processors were then given to the software team, who built the most efficient application they could based on the hardware constraints they were given.

Jim explained a new model began emerging around 2005 that started with cell phones. Now, the software and user experience were the driving specification and the processor was built to support that specification. Essentially, the handoff arrows reversed in the product development lifecycle. If software now defined the hardware, there is opportunity for software to also define power consumption for that hardware. This new design paradigm further fueled the focus and innovation occurring at AGGIOS.

Now, there was an opportunity to quantify power savings based on software optimization. Savings in the double-digit percentages became possible and this provided the opportunity for more innovation and optimization. You get what you measure, so to speak.  Against this backdrop AGGIOS and its software defined energy management approach began to grow. I poked at competition a bit with Jim. AGGIOS appears to be singular in its focus on software defined energy management, why was that?

Jim pointed out that markets don’t occur overnight, they take time to grow. He recalled the decade or more that was required for Apache to create a transistor-level power optimization market. Today, there are many drivers for power optimization and energy management. The aerospace and defense sector has a significant focus on the problem. So does industrial test and measurement. Hand-held devices are everywhere, and battery life is a key usability item. And of course, there is constant focus on power reduction in the data center and the edge. AGGIOS is simply ahead of the curve.

There were more stories and more insights in my conversation with Jim. Perhaps the topic of a future posts. After my conversation, I had a better perspective on the history and significance of power optimization.

[post_title] => The History and Significance of Power Optimization, According to Jim Hogan [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => the-history-and-significance-of-power-optimization-according-to-jim-hogan [to_ping] => [pinged] => [post_modified] => 2020-11-17 10:59:38 [post_modified_gmt] => 2020-11-17 18:59:38 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292786 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 1 [filter] => raw ) [5] => WP_Post Object ( [ID] => 292896 [post_author] => 28 [post_date] => 2020-11-13 06:00:04 [post_date_gmt] => 2020-11-13 14:00:04 [post_content] => Defacto CEO Interview Chouki Aktouf "For more than 18 years, we never stopped innovating at Defacto. We are aware of EDA Mantra “Innovate or Die!”. Innovation is in our DNA, and we never stopped adding new automated capabilities to the SoC design community to help facing complexity and cost challenges, which increase every year." Before founding Defacto in 2003, Dr. Chouki Aktouf was an associate professor of Computer Science at the University of Grenoble – France, and the dependability research group leader. He holds a Ph.D. in Electric Engineering from Grenoble University We heard a long time ago about the Defacto RTL DFT solution and, since our last interview, Defacto’s SoC Integration solutions at RTL seem to create a lot of Buzz within the designers’ community. Would you please tell us more? Yes, we started as a DFT tool provider more than 18 years ago currently main offer is in the area of SoC integration at RTL, where we help our customers build a unified design flow to start the design assembly and SoC integration process pre-synthesis covering RTL but not only by including other design collaterals such as UPF, SDC, and IPXACT. Beyond the automation we provide, we enable a high degree of customization, including rich APIs beyond Tcl, like Python and Java. In summary, Defacto simplifies the implementation process pre-synthesis by taking care of the RTL, including system Verilog and all the design data correlated to the RTL. A typical example is the Accellera standard IPXACT used to describe, integrate, and share IP and sub-systems. Defacto now has a complete offer where IPXACT and RTL are tight to each other in a one and a unified SoC implementation platform.   You talk about IPXACT for integration and, we heard about the Magillem acquisition. Is it a good opportunity for you to help customers in this area? Customers are telling us that they don’t want IPXACT to be decorrelated to the RTL, and they are pushing us to cover the IPXACT related needs not only in terms of coherency checks and view generation but, more importantly, during the RTL SoC  integration process. The good news is that we are ready to answer the IPXACT Design assembly and SoC Integration needs. We already count daily users for real projects. In summary, we are helping both new IPXACT adopters who need a smooth, reliable migration in full compliance with RTL design flows and companies who already consider IPXACT as a golden format. In other words, we believe we are covering current market needs, and we are even anticipating the future. Indeed, being an active Accellera member, we capture customer needs beyond current IPXACT 2009 and 2014 standards.   You talk about UPF and SDC. How do you manage them during the integration process? Do you update them as well? SDC and UPF are necessary to design collaterals that are key during the SoC implementation process. Managing RTL alone is not enough. Updating UPF and SDC files when RTL changes is a painful design task that is traditionally manual.  Defacto provides automation to cover checking between RTL and SDC/UPF but also updating UPF and SDC along with RTL changes and many other related automated capabilities.   Your platform seems to be a complete solution for SoC Integration, covering all the needs at Front-end. Who is the typical customer of Defacto? Most SoC companies and major IP providers build SoC chips for their customers who need to bring more automation into their design flows. Today we are in a situation where most SoC companies buy IPs from 3rd parties, build their own IPs, reuse part of previous projects and nothing is packaged the same way.  It becomes a mess when it’s time to realize the SoC Assembly. Using the flexibility of our platform, designers can start building their SoC faster and earlier. We are proud to count as customers major semiconductor companies leading the chip market of communication, processors, AI, IoT, etc.   What makes customers go with your solution, what do they find in your company that doesn’t exist in the other EDA vendors like the majors? Our solution has reached a maturity level that makes our customers more confident to manage aggressive PPA requirements when using Defacto. We already contributed in silicon success for so many different projects including leading edge technologies. We are not competing with Majors EDA companies. We strongly believe we are complementary to their EDA tools in the area of the SoC integration and design assembly. Also since Defacto’s STAR is more a platform than a point tool, a user finds several customization ways of the used features including the API languages. In summary our customers are telling us they like the flexibility and the ease use of our tools. Even the migration of their internal scripts, it is straightforward when switching to Defacto’STAR.   What are the plans for Defacto in the coming years? Defacto is growing and will continue to grow. We are present in almost all territories with local technical expertise. In the coming months, we are preparing new announcements of our STAR Platform with new capabilities that will continue putting STAR much ahead as the “De facto” SoC Integration and Assembly solution pre synthesis.  Finally, when using Defacto our customers know they will get best in class combination: support and product quality.  To protect this “support & quality” brand, we will not stop improving daily our support by making our reactivity even better and also the quality of our tools  by strengthening our internal QA process.   [post_title] => CEO Interview: Dr. Chouki Aktouf of Defacto [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => ceo-interview-dr-aktouf-of-defacto [to_ping] => [pinged] => [post_modified] => 2020-11-16 07:57:30 [post_modified_gmt] => 2020-11-16 15:57:30 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292896 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [6] => WP_Post Object ( [ID] => 292978 [post_author] => 13 [post_date] => 2020-11-12 10:00:42 [post_date_gmt] => 2020-11-12 18:00:42 [post_content] => Design for test (DFT) requires a lot of up-front planning that can be difficult to alter if testing needs or performance differ from initial expectations. Hierarchical methodologies help in many ways including making it easier to reduce on chip resources such as the number of test signals. Also, hierarchical test allows for speed-ups from parallel testing of separate blocks. MUX’ing of test signals helps deal with limited test pins on SOCs, and also reduces wiring overhead. Yet with each of these advantages comes the need to plan accordingly. Mentor has just announced what they call Streaming Scan Network (SSN) in their Tessent product line that promises to offer increased flexibility and performance. Tessent’s SSN offers support for implementation of a specialized network for carrying test data within an SOC. [caption id="attachment_292980" align="aligncenter" width="1025"]Streaming Scan Network 1 Streaming Scan Network[/caption] While at glance it might seem that a Network On Chip (NOC) similar to those used for block level data buses would suffice, however Mentor has developed a highly optimized solution that better meets the needs of DFT in several clever ways. The Streaming Scan Network bus width is independent of the number of the block level scan pins. For instance, a 4 bit wide SSN bus can carry 7 bits for one block and 5 for another, interleaving the bits on the SSN bus. In fact, the SSN bus could even be 1-bit wide if needed and still be used for cores with any number of test pins. There is a controller at each core node that manages the incoming and outgoing test data and transfers it to and from the block’s scan pins. The controllers have their own command line that directs their activity. Because once streaming starts there is no header information required, the SSN bus is carrying 100% payload. This is why for test SSN is a better solution than traditional NOCs. The grouping of cores for parallel testing can be easily reconfigured because the targeting of test data is handled by the node controllers. So, if in the late stages of product development, a specific block’s test vector size increases, no hardware changes are needed. Also scan and capture can now be handled flexibly and do not have to align with other blocks being tested at the same time. If there are blocks that require larger vectors, they can get priority, so their tests can complete sooner. This makes it possible to optimize and save tester time. So, what are the results of using the Streaming Scan Network? Mentor worked extensively with Intel prior to the announcement. In fact, Intel published a paper at the 2020 ITC that goes into the details of the improvements they observed. Intel reports that they found that SSN reduced test data volumes by 36 to 43%, reduced test cycles by 16 to 43%. They were able to run the steps in the design and retargeting flow between 10-20X faster when compared to their previous methodology. Mentor claims that DFT development time can be cut in half or more with the application of Streaming Scan Networks. Also, because it also supports abutment-based design styles, it is useful in many of the newer tile based designs found in AI and other parallel processing applications. Mentor has shown a consistent history of aggressive technology development in test. The recent advances in their Tessent product are impressive. Although, in hindsight it seems inevitable that a packet based methodology would be advantageous for DFT, Mentor has taken the time to develop a well thought out approach that is well suited for test in particular. More information about Mentor’s Streaming Scan Network in Tessent can be found on the Mentor website. [post_title] => Mentor Offers Next Generation DFT with Streaming Scan Network [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => mentor-offers-next-generation-dft-with-streaming-scan-network [to_ping] => [pinged] => [post_modified] => 2020-11-14 12:43:53 [post_modified_gmt] => 2020-11-14 20:43:53 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292978 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [7] => WP_Post Object ( [ID] => 292619 [post_author] => 16 [post_date] => 2020-11-12 06:00:40 [post_date_gmt] => 2020-11-12 13:00:40 [post_content] => Paul Cunningham (Verification CVP/GM at Cadence) initiated our monthly Innovation in Verification blog to hunt for novel ideas in verification, breaking past the usual steady, necessary but undramatic pace of incremental advances. I attended a couple of sessions from DVCon Europe recently, and was encouraged to hear a couple of talks with a similar mindset. The opening keynote was delivered by Moshe Zalcberg, CEO of Veriest on what ideas hardware design and verification might borrow from software. Moshe covered a lot of territory – open source design and tooling, use of Python, Agile, more effective use of data and AI. I’d like to look here at the topic of Agile/DevOps for hardware. Particularly since Vicki Mitchell, an engineering VP at Arm, followed with a later keynote on how she is applying these today in Arm. Agile and DevOps for Hardware

Waterfall versus Agile

I’d better start with a little explanation, following Moshe’s talk. Consider traditional waterfall development, the approach most of us use in design and verification today. From requirements gathering to design, implementation and verification, and ultimately to delivery, in that sequence. Here, the product is not really usable until near the end. Agile methods aim to improve on waterfall approaches though continuous delivery of value, delivering working code frequently, and maintaining a constant pace of delivery. Developers build code in short cycles called sprints, available at multiple points through the complete cycle. Shift-left is a compressed waterfall. In contrast, Agile breaks up the goal by code features and aims to complete a group of features as well as possible on each sprint drop. If it’s for a testbench for example, each sprint should deliver a working testbench (or family of testbenches) for some set of features.

How Agile helps

These practices have already become common in software development. Software team leaders assert that an agile flow provides higher quality results because developers have to fully test what they build in the current sprint. It also provides better schedule predictability and difficult problems are surfaced more quickly for resolution. Obviously you have to embed testing tightly in development in this approach – unit testing, coding standards, static analysis and so on. There are tons of unit testing frameworks in the software world to help automate this task.

Application in Arm

In hardware design and especially verification, Moshe admits we are in early days of adoption of such practices. However it is starting to happen, notably in Arm in the systems group. Vicki Mitchell, VP of central engineering for that group gave a second keynote on how they’re using DevOps in that role, also in supporting customers through reference design system verification for example. She brings to this role a lot of background in running software engineering organizations at other companies such Intel. Vicki mentioned, incidentally, a key motivation for Agile approaches – lack of clear requirements and user feedback. Customers are figuring out on-the-fly what they need, and competitors aren’t standing still. That creates much more churn in development and a greater need for agility. Which leads to a need in Arm’s eyes to make agility actionable. Vicki talked particularly about DevOps rather than Agile. These two processes look very similar to a simpleton like me. My takeaway is that DevOps has an in-house focus (development + operations, aka build, regression, delivery etc). It aims for very quick feedback and it has a big focus on automation.

Arm DevOps automation

What I found particularly interesting in Vicki’s talk was Arm’s implementation and learning for continuous integration. Their gatekeeper flow monitors as you check in a change with integration tests. They use change-set checks to determine which tests should be run and will up-vote or down-vote your submission on each test. Test sets bloat fairly quick in this automation. They apply machine learning to periodically cull down to an optimized set. They’ve also developed tools to automate building integration tests. She summed up by noting that they’ve been able to improve scheduling and provide more frequent deliveries to stakeholders. The CPU team at Arm (Austin I think) is now piloting a similar program. Interesting insights. You can learn a lot more from the talks themselves. These are still available as recordings from DVCon Europe, through November 23rdThis is the Moshe keynote, and this is the Vicki keynote.   [post_title] => Agile and DevOps for Hardware. Keynotes at DVCon Europe [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => agile-and-devops-for-hardware-keynotes-at-dvcon-europe [to_ping] => [pinged] => [post_modified] => 2020-11-14 12:44:16 [post_modified_gmt] => 2020-11-14 20:44:16 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292619 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [8] => WP_Post Object ( [ID] => 292703 [post_author] => 11830 [post_date] => 2020-11-11 10:00:08 [post_date_gmt] => 2020-11-11 18:00:08 [post_content] =>

 

SiFive Expands RISC V Technology and its Ecosystem at the Fall Linley Processor ConferenceAs the Linley Fall Processor Conference winds down, there are certain presenting companies that left a lasting impression.  SiFive is one of those companies. On October 21, SiFive introduced the newest member of the SiFive Intelligence family of processor coresSiFive Intelligence family of processor cores, based on the RISC-V ISA and the RISC-V Vector (RVV) extension. And then on October 29 they presented details of the highly anticipated RISC-V PC ecosystem. So, SiFive was busy expanding RISC-V technology and its ecosystem. Here are some details of both presentations.

Extending AI SoC Design Possibilities Through Linux-Capable Vector Processors

This presentation was given by Krste Asanović, SiFive Chief Architect & Co-Founder and Co-Inventor of RISC-V. Krste began with a review of the challenges associated with AI SoC design. These include:

  • Multiple bandwidth-hungry subsystems
  • Multiple proprietary instruction sets for deep learning accelerators
  • Poor memory-bandwidth utilization
  • Complex memory crossbar
  • Power optimization difficult to implement

There are also software challenges for these designs, including:

  • Multiple proprietary accelerator instruction sets
  • Multiple proprietary API’s and outdated libraries
  • New techniques such as deep compression or Winograd transform not supported
  • Memory hierarchy doesn’t match new algorithm requirements
  • Poor compiler support, requires programming at a low level
  • Power optimization difficult to implement

Krste then presented the newest member of the SiFive Intelligence family of processor cores to address these challenges. The family is based on an open industry standard ISA (RVV v1.0) to prevent vendor lock-in and enable rich ecosystem for AI. Krste reported this is the first commercially available processor core IP based on the expected final RVV 1.0 specification.

He explained these cores deliver scalable performance to meet AI processing requirements from extremely low power to high performance compute applications. The multi-core architecture can integrate Linux capable or real-time cores with accelerators to provide performance scaling.  It also provides efficient memory hierarchy that maximizes data reuse. The single ISA enables a simple and efficient programming model that allows tuning algorithms for both performance and low power.

Security is always a discussion point for these applications, and SiFive provides comprehensive security support enabled by SiFive WorldGuard, a capability of SiFive Shield to provide true hardware isolation for whole SoC security while enabling software portability. You can see a video overview of SiFive WorldGuard here. There is also an advanced trace and debug solution, making the Intelligence family quite robust.  Krste shared the roadmap for this technology, shown below.

[caption id="attachment_292788" align="aligncenter" width="525"]SiFive Intelligence Roadmap SiFive Intelligence Roadmap[/caption]

Creating a RISC-V PC Ecosystem for Linux Application Development

This presentation was given by Dr. Yunsup Lee, SiFive CTO & Co-Founder and Co-Inventor of RISC-V. Yunsup detailed what embedded developers need, which includes:

  • Industry Standard Form Factor
  • Advanced Features
  • Linux-Capable Development Platform
  • Out-of-the Box Software
  • IP Evaluation
  • Expansion

Yunsup explained that SiFive delivers these capabilities with its HiFive Unmatched, a development board for a Linux-based PC that uses its RISC-V processors. A photo of the development board and a summary of key features is shown below.

[caption id="attachment_292789" align="aligncenter" width="525"]SiFive HiFive Unmatched SiFive HiFive Unmatched[/caption]

Yunsup detailed some of the capabilities of the SiFive FU740 SoC on this board. These include:

  • SiFive 7-Series Multi-Core Application Processor
    • 64-Bit 8-Stage Dual-Issue, Superscalar RISC-V Core
  • Application Core Complex
    • 4x SiFive U74 Cores
    • RV64GC (RV64IMAFDC)
    • 32KB I$ Per Core
    • 32KB D$ Per Core
  • Single Embedded S7 Core
    • RV64IMAC
    • 16KB I$
    • 8KB DTIM
  • 2MB Coherent Banked L2$
  • Integrated PCIe® Gen 3, DDR4, & I/O

Yunsup mentioned a short video demonstration of HiFive Unmatched used as a professional developer platform. He explained the video will cover:

  • Native compilation
    • Video application
    • Example benchmark
  • GPU accelerated video playback
  • Web browser functionality

The video was posted to the SiFive YouTube channel after the presentation and can be viewed here.

Also available is the Freedom E SDK, which is a repository of demo programs, industry standard benchmarks and board support packages (BSPs) for SiFive’s hardware platforms. The package is available on GitHub here. Yunsup explained the development board will be available worldwide Q4’20 for $665USD.  So, SiFive was indeed busy expanding RISC-V technology and its ecosystem.

[post_title] => SiFive Expands RISC-V Technology and its Ecosystem at the Fall Linley Processor Conference [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => sifive-expands-risc-v-technology-and-its-ecosystem-at-the-fall-linley-processor-conference [to_ping] => [pinged] => [post_modified] => 2020-11-14 12:44:42 [post_modified_gmt] => 2020-11-14 20:44:42 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292703 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [9] => WP_Post Object ( [ID] => 292506 [post_author] => 28 [post_date] => 2020-11-11 06:00:15 [post_date_gmt] => 2020-11-11 14:00:15 [post_content] => I was reading the S2C press release announcing their new FPGA prototyping platform based on the Xilinx UltraScale+ VU19P FPGA, and how the new FPGA will accelerate billion gate FPGA prototyping, and I was struck by the stunning implications of this announcement.  Not that billion gate SoC designs can now be prototyped with FPGAs, the larger FPGA prototyping providers have been talking about this for a while.  I was struck by the trajectory that FPGAs are on to hugely simplify FPGA prototyping.  Twenty years ago, early FPGAs supported about 5K ASIC gates (Xilinx XC30902) and now the VU19P FPGA boasts an estimated 50M ASIC gates!  That’s 10,000 times more ASIC gates from a single FPGA device in 20 years! Prototyping with the Latest and Greatest Xilinx FPGAs
Request a Quote
Look, the biggest challenge for FPGA prototyping is getting an SoC design working in FPGAs fast.  Not only to minimize the set-up effort of just one of the verification tools in the verification toolbox, but also to minimize the risk that the FPGA prototype never produces the expected pre-silicon verification ROI.  Generally, bigger FPGAs reduces the number of FPGA devices needed to prototype an SoC design.  The previous largest Xilinx FPGA, the UltraScale VU440, has an estimated capacity today of about 30M ASIC gates and it was announced in 2015. If the new UltraScale+ VU19P delivers the expected 49M ASIC gate capacity, that’s 1.7 times more ASIC prototyping gates from a single FPGA in 5 years, and if the semiconductor industry is true to form, it’s not unreasonable to expect the FPGA gate capacity growth to be non-linear.  So, simply using the same growth factor, it’s easy to project 80M ASIC gate FPGAs is less than 5 years, and 140M ASIC gate FPGAs is less than 10 years. You can see where this thinking is going – we might be able to prototype a billion gate SoC design with 5 or 7 FPGAs in less than 10 years!  Then, the job of getting an SoC design into an FPGA prototype will be super bigly simplified – or maybe just routine.  The task of partitioning billion gate designs into multiple FPGAs gets much easier. The prototype performance gets better because most of the interconnect would be contained within an FPGA.  And, the cost of ownership should decline to the point where FPGA prototyping for large SoC designs approaches the pervasiveness that we see today for smaller SoC designs that fit into one or a few FPGAs. If you are a skeptic, and are doubting that the FPGA companies can deliver on this aggressive capacity growth curve, take a look at the highly advanced packaging technology that Intel and Xilinx are using to produce their largest FPGAs today.  The trending approach is to use logic fabric “chiplets” to increase yield on advanced silicon nodes and to reduce cost. Combine this with 3D silicon interconnect, and heterogeneous die in the same package, and voila! – they could continue down this path all day long, possibly with a faster ASIC gate capacity growth factor than the last 5 years.  As always, I’m betting on technology and a stellar future for FPGA prototyping. Xilinx Delivers the Industry's First 4M Logic Cell Device, Offering >50M Equivalent ASIC Gates and 4X More Capacity than Competitive Alternatives Xilinx XC3000 FPGA Product Description S2C Accelerates Billion Gate FPGA Prototyping with Xilinx Virtex UltraScale+ VU19P Based Systems
About S2C
S2C, is a global leader of FPGA prototyping solutions for today’s innovative SoC/ASIC designs. S2C has been successfully delivering rapid SoC prototyping solutions since 2003. With over 500 customers and more than 3,000 systems installed, our highly qualified engineering team and customer-centric sales team understands our users’ SoC development needs. S2C has offices and sales representatives in the US, Europe, Israel, China, Korea, Japan, and Taiwan. For more information please visit www.s2cinc.com. [post_title] => Prototyping with the Latest and Greatest Xilinx FPGAs [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => prototyping-with-the-new-xilinx-fpgas [to_ping] => [pinged] => [post_modified] => 2020-11-14 12:45:17 [post_modified_gmt] => 2020-11-14 20:45:17 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=292506 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 1 [filter] => raw ) ) [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object ( [ID] => 293033 [post_author] => 11830 [post_date] => 2020-11-16 10:00:28 [post_date_gmt] => 2020-11-16 18:00:28 [post_content] =>

Powering the Next Generation of Hearables and Wearables with ChipusChipus is an interesting company. It’s been around since 2008 and focuses on mixed-signal ASICs, intellectual property blocks and IC design services. They are headquartered on the island of Florianopolis, which is described as the most dense startup ecosystem in Brazil. The company has substantial skills in analog and mixed signal designs, but they’ve also successfully delivered designs in FinFET technologies from RTL to tapeout. Having spent time in analog, mixed signal and FinFET design, I can tell you it’s a rare blend of skills to be able to address all of these disciplines. You can learn more about Chipus from the interview Dan Nenni did with their CEO, Murilo Pilon Pessatti here. Recently, I had an opportunity to preview a webinar that discusses powering the next generation of hearables and wearables with Chipus. IoT is hot, so this one certainly caught my attention.

[caption id="attachment_293062" align="alignright" width="106"]Murilo Pessatti Murilo Pessatti[/caption]

The webinar is presented by Murilo Pessatti, CEO of Chipus and Heider Marconi, manager of technical sales at Chipus. Murilo co-founded Chipus. He started working with semiconductor design more than 15 years ago. Between 2003 and 2005, he worked in the power management group of Chipidea Microelectronics, Portugal (acquired by Synopsys). After his experience in Europe, Murilo joined CEITEC (a Brazilian IDM Company) as technical leader and project manager for three years. He holds an MSEE degree in analog IC design from UNICAMP (State University of Campinas) and also has background in project management.

[caption id="attachment_293063" align="alignright" width="105"]Heider Marconi Heider Marconi[/caption]

Heider was previously CEO of DFchip, a design house and IP provider focused on developing efficient and low power circuits. He joined Chipus three years ago. Both these gentlemen have substantial background in power management and this was the focus of the webinar.

The webinar began with an overview of the hearables and wearables market and Chipus from Murilo. While these kinds of devices have been around for a long time, they are now becoming quite ubiquitous and consumers are demanding smaller, lighter and more comfortable devices. Success in this market will be decided by fashion trends and the devices themselves must accommodate those trends.

Applications include entertainment, health monitoring and augmented reality. Murilo shared some market size data, which is absolutely staggering.  You’ll need to watch the webinar to see the numbers for yourself. Murilo also discussed some work Chipus is doing with GLOBALFOUNDRIES on their 22nm FD-SOI technology, called 22FDX. After a discussion of market dynamics, Murilo handed the presentation over to Heider, who presented a comprehensive power management IP solution from Chipus based on GF 22FDX.

This IP handles a great deal of the power management functions for IoT class devices, including battery charging and battery management as well as overall power management for the chip. Since every design is different, the IP is highly configurable, allowing substantial power management offloading from the main processing portion of the design. Heider goes into a lot of detail, you really need to see the webinar and check it out.

The webinar concludes with a robust Q&A, addressing some very relevant application-level questions. The webinar replay is available HERE. I was amazed at the size of this segment of the IoT market. It’s definitely worth the time to see how Chipus is powering the next generation of hearables and wearables.

About Chipus

Chipus Microelectronics (ISO 9001:2015 certified) is a semiconductor company focused on the development of mixed-signal ASICs, intellectual property (IP) blocks and IC design services.

The company has more than 200 analog IP blocks in process nodes from 22nm to 0.35um of various foundries. Since its foundation in 2008, Chipus has worked with customers worldwide (South and North America, Europe, and Asia) with firm commitment and flexible client support.

Besides analog and mixed-signal expertise, Chipus also offers custom digital IC design services having successfully delivered designs in FINFET technologies from RTL to backend.

Headquartered in Florianópolis, Brazil, Chipus has a US subsidiary in Silicon Valley and sales teams in both USA and Europe.
 
 
 
 
 
 
 
 

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Powering the Next Generation of Hearables and Wearables with Chipus

Powering the Next Generation of Hearables and Wearables with Chipus
by Mike Gianfagna on 11-16-2020 at 10:00 am

Powering the Next Generation of Hearables and Wearables with Chipus

Chipus is an interesting company. It’s been around since 2008 and focuses on mixed-signal ASICs, intellectual property blocks and IC design services. They are headquartered on the island of Florianopolis, which is described as the most dense startup ecosystem in Brazil. The company has substantial skills in analog and mixed… Read More


Webinar: Increase Layout Team Productivity with SkillCAD

Webinar: Increase Layout Team Productivity with SkillCAD
by Daniel Nenni on 11-16-2020 at 6:00 am

Header Webinar 1

The Cadence Virtuoso Design System has been one of the premier Integrated Circuit design systems for many years and is used by most major semiconductor companies.  While it is powerful and versatile, it is often not optimized for certain complex, repetitive and time-consuming layout design tasks.

The founder and president … Read More


TSMC to Build first US Fab in Arizona!

TSMC to Build first US Fab in Arizona!
by Daniel Nenni on 11-15-2020 at 10:00 am

TSMC North America SemiWiki

Well, it’s official, the TSMC Board of Directors approved an investment to establish a wholly-owned subsidiary in Arizona with a paid-in capital of $3.5 billion. As history shows the investment may be more than that but $3.5B is a great starting point. This is being discussed in the SemiWiki Forum  and I have been gathering inside… Read More


2021 will be the year of DRAM!

2021 will be the year of DRAM!
by Robert Maire on 11-15-2020 at 6:00 am

Robert Maire Bloomberg

2020 has been a NAND growth year-2021 will be the year of DRAM. While foundry logic has gotten all the credit in 2020 the reality is that NAND has been up 2X in 2020 for semiconductor equipment provider Applied Materials (AMAT). It is expected that NAND will be flat in 2021 while DRAM will take over the growth slot with foundry/logic … Read More


The History and Significance of Power Optimization, According to Jim Hogan

The History and Significance of Power Optimization, According to Jim Hogan
by Mike Gianfagna on 11-13-2020 at 10:00 am

Jim Hogan

Power seems to be on everyone’s mind these days. Hyperscale data centers worry about operating costs unless power is optimized. The AI accelerators in the Edge can’t be effective without optimized power. Advanced 2.5 and 3D packages simply can’t remove the heat unless power is optimized.  And then there’s all those gadgets we … Read More


CEO Interview: Dr. Chouki Aktouf of Defacto

CEO Interview: Dr. Chouki Aktouf of Defacto
by Daniel Nenni on 11-13-2020 at 6:00 am

Defacto CEO Interview Chouki Aktouf

“For more than 18 years, we never stopped innovating at Defacto. We are aware of EDA Mantra “Innovate or Die!”. Innovation is in our DNA, and we never stopped adding new automated capabilities to the SoC design community to help facing complexity and cost challenges, which increase every year.”

Before founding Defacto… Read More


Mentor Offers Next Generation DFT with Streaming Scan Network

Mentor Offers Next Generation DFT with Streaming Scan Network
by Tom Simon on 11-12-2020 at 10:00 am

Streaming Scan Network

Design for test (DFT) requires a lot of up-front planning that can be difficult to alter if testing needs or performance differ from initial expectations. Hierarchical methodologies help in many ways including making it easier to reduce on chip resources such as the number of test signals. Also, hierarchical test allows for speed-ups… Read More


Agile and DevOps for Hardware. Keynotes at DVCon Europe

Agile and DevOps for Hardware. Keynotes at DVCon Europe
by Bernard Murphy on 11-12-2020 at 6:00 am

Agile and DevOps for Hardware

Paul Cunningham (Verification CVP/GM at Cadence) initiated our monthly Innovation in Verification blog to hunt for novel ideas in verification, breaking past the usual steady, necessary but undramatic pace of incremental advances. I attended a couple of sessions from DVCon Europe recently, and was encouraged to hear a couple… Read More


SiFive Expands RISC-V Technology and its Ecosystem at the Fall Linley Processor Conference

SiFive Expands RISC-V Technology and its Ecosystem at the Fall Linley Processor Conference
by Mike Gianfagna on 11-11-2020 at 10:00 am

SiFive Expands RISC V Technology and its Ecosystem at the Fall Linley Processor Conference

 

As the Linley Fall Processor Conference winds down, there are certain presenting companies that left a lasting impression.  SiFive is one of those companies. On October 21, SiFive introduced the newest member of the SiFive Intelligence family of processor coresSiFive Intelligence family of processor cores, based on… Read More


Prototyping with the Latest and Greatest Xilinx FPGAs

Prototyping with the Latest and Greatest Xilinx FPGAs
by Daniel Nenni on 11-11-2020 at 6:00 am

Prototyping with the Latest and Greatest Xilinx FPGAs

I was reading the S2C press release announcing their new FPGA prototyping platform based on the Xilinx UltraScale+ VU19P FPGA, and how the new FPGA will accelerate billion gate FPGA prototyping, and I was struck by the stunning implications of this announcement.  Not that billion gate SoC designs can now be prototyped with FPGAs,… Read More