Synopsys IP Banner SemiWiki

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                    [post_content] => Central America and Mexico Tour SiFive SemiWiki

We’re confirming seats for our first two SiFive Tech Symposiums in 2020. The first will take place in San José, Costa Rica on February 25, and the second will be in Mexico City, Mexico, on February 28. Just like our 2019 symposiums, these events are designed to engage the global hardware community in the RISC-V ecosystem, and to further promote the revolution that’s taking place within the semiconductor industry.

We’re proud to have Western Digital is our co-host in Costa Rica, and the Computing Research Center at CIC-IPN is our co-host in Mexico. Both events will feature presentations on RISC-V development tools, platforms, core IP and SoC IP, as well as talks about the exciting opportunities stemming from RISC-V, and the leading-edge research taking place in academia. Both events will also include a hands-on workshop where attendees will have the opportunity to configure their own RISC-V core and bring up on an FPGA.

Attendance is free, but registration is required.

San José, Costa Rica

Co-located with LASCAS 2020

Mexico City, Mexico

Instituto Politécnico Nacional/National Polytechnic Institute of México

The learn more about other SiFive Tech Symposiums taking place throughout the world in 2020, please visit the website, and check back often for updates. We look forward to seeing you soon!

About RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 500 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.

About SiFive
SiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 14 offices worldwide, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, www.sifive.com.

 
                    [post_title] => The First SiFive Tech Symposiums of 2020 are Fast Approaching – We’ll be in San José, Costa Rica, and Mexico City This Month
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                    [post_content] => DVCon 2020 SemiWikiAre you ready for the premier conference for functional design and verification of electronic systems?

Sponsored by Accellera Systems Initiative, DVCon is an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies.

This year at DVCon, you’ll find Mentor experts featured prominently throughout the conference program discussing the latest in Portable Stimulus, UVM, Formal, CDC, Low- Power Verification, High-Level Synthesis, and much more.

A full list of Mentor activities, can be found here.

SPONSORED LUNCHEON
Optimizing Time to Bug, Don’t Panic!!!
Thursday, March 5 | 11:45am – 12:45am | Sierra

Come join Tom Fitzpatrick, Strategic Verification Architect at Mentor, a Siemens Business, as he explores the myriad factors that contribute to verification complexity and how the changing landscape of electronics will expose new challenges in the continuing quest to find and eliminate bugs as early and effectively as possible.

FEATURED TUTORIAL
Application Optimized HW/SW Design & Verification of a Machine Learning SoC
Thursday, March 5 | 8:30am – 11:30am | Donner

This tutorial walks through the process of migrating an algorithm from generic software to a hardware implementation customized to the specific requirements of your system; making intelligent trade-offs between hardware and software along the way. It will explain the tools and techniques needed to go from “Software to Systems” and cover a broad range of solutions including simulation, emulation, prototyping, and High-Level Synthesis to design and verify SoCs and the software that runs on them.

FEATURED PANEL
Predicting the Verification Flow of the Future
Wednesday, March 4 | 1:30pm – 2:30pm | Oak/Fir

Moderator Jean-Marie Brunet from Mentor, a Siemens Business, will take a panel of verification experts on an exploration of what the verification environment of the future will look like. They will attempt to predict the longevity of simulation and formal verification and determine how far emulation will be able to extend through the entire verification flow. The role of standards will be addressed, as will when analog will have a place in digital functional verification.

SHORT WORKSHOPS
How HLS and SystemC is Delivering on its Promise of Design and Verification Productivity 
Monday, March 2 | 3:30pm – 5:00pm | Oak

Mind the GAP(s): Closing and Creating GAPS between Design and Verification 
Thursday, March 5 | 1:00pm – 2:30pm | Siskiyou

PAPER SESSIONS
Designing PSS Environment Integration for Maximum Reuse
Tuesday, March 3 | 9:00am – 10:30am | Fir

UVM – Stop Hitting Your Brother Coding Guidelines
Tuesday, March 3 | 3:00pm – 5:00pm | Oak

Multi-Level Replay of VIP Models in Isolation from Original Design Verification Environment to Enhance Protocol Analysis and Debug
Tuesday, March 3 | 3:00pm – 5:00pm | Fir

UPF 1.0, UPF 2.0, UPF 2.1, UPF 3.0, and Now UPF 3.1: The Big Q “Which is the Right Standard for My Design?"
Tuesday, March 3 | 3:00pm – 5:00pm | Monterey/Carmel

Did Power Management Break My CDC Logic? An Integrated Approach to Power Domain and Clock Domain Crossing Verification
Tuesday, March 3 | 3:00pm – 5:00pm | Monterey/Carmel

Systematic Methodology to Solve Reset Challenges in Automotive SoCs
Wednesday, March 4 | 3:00pm – 4:30pm | Monterey/Carmel

Scalable Reset Domain Crossing Verification Using Hierarchical Data Model
Wednesday, March 4 | 3:00pm – 4:30pm | Monterey/Carmel

SystemVerilog Constraints: Appreciating What You Forgot in Class to Get Better Results
Wednesday, March 4 | 3:00pm – 4:30pm | Oak

POSTER SESSIONS
Tuesday, March 3 | 10:30am – 12:00am | Gateway Foyer

4.3 - Covergate: Coverage Exposed

4.8 - How UPF 3.1 Reduces the Complexities of Reusing Power Aware Macros

4.11 - Are You Safe Yet? Safety Mechanism Insertion and Validation

4.14 - Deadlock Verification for Dummies - The Easy Way Using SVA and Formal

EXHIBIT FLOOR
You’ll find Mentor experts in booth #404 presenting daily theater sessions and running the latest Enterprise Verification Platform demos across Emulation, Low Power, Formal, Portable Stimulus, High-Level Synthesis, Verification IP, Debug, and more!

Mentor has pioneered technology to close the design and verification gap to improve productivity and quality of results. Catapult High-Level Synthesis for C-level verification and PowerPro for power analysis; Questa for simulation, low-power, VIP, CDC, Formal and support for UVM and Portable Stimulus; Veloce for hardware emulation and system of systems verification, unified with the Visualizer debug environment.
                    [post_title] => Mentor at DVCON 2020!
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                    [post_content] => Semiconductor Weekly Summary 1

The new coronavirus outbreak or COVID-19 outbreak, as it is now officially called, continues to dominate the news again this week as currently there is no end forecast to the outbreak, and infection numbers continue to rise. This will have an impact on semiconductor supplies in the coming months and into Q2 as the necessary restrictions to try to contain the disease cause Chinese companies struggle to be allowed to reopen after the extended Chinese new year holiday and to also get workers allowed back from other parts of China, especially for the smaller companies. This will have a knock on impact not just on semiconductor supplies from China in the coming months but also on supplies of materials and consumables to non Chinese semiconductor manufacturing companies. Let’s hope the COVID-19 outbreak comes under control soon and all my colleagues and acquaintances and families stay safe and healthy throughout this difficult period.

Chinese leading wafer foundry SMIC said on Friday that it will double its capital spending in 2020 and expects revenue to grow 10% despite the COVID-19 outbreak, but SMIC did also warn that the worst may yet be to come from the COVID-19 outbreak as implications ripple through the supply chain.

The impact of the COVID-19 outbreak is also being felt worldwide as the organizers of Mobile World Congress 2020 have cancelled this years event. Although the event is being held in Barcelona, most companies have travel restrictions in place and too many companies pulled out of the event.

US lighting companies are expecting delayed product supply due to the COVID-19, with US companies Cooper Lighting Solution and Satco both posting notices to their customers on possible interruption of supplies.

A survey by LEDinside magazine on the impact of COVID-19 on the Chinese LED industry showed that only 28% of companies think they will still make a profit despite the COVID-19 outbreak, whilst 38% think they will make a loss. If companies are allowed to resume production on Feb 17th 44% of companies expect the work resume rate to 50~70%, whilst 27% of companies expect the work resume rate to be below 50%.

In other news...

Whilst last year was a challenging year for most semiconductor companies, TSMC managed to buck the trend especially in the 2nd half. In recognition of last year's record revenue, TSMC ‘s board has approved to pay TSMC’s 45,000 employees an average annual bonuses of US$33,000. The bonus will be paid in July. The total bonus amount to be paid out is 1.7% lower than 2018 as it reflects the 1.7% lower profit margin last year. TSMC’s board also approved a US6.7billion budget for advanced process and capacity expansion this year.

Taiwanese foundries and backend subcons published their monthly revenue figures last week. TSMC continued the trend from 2nd half last year.  TSMC posted monthly revenue of US$3.45billion (NT$103.7billion) up 0.4% on sequentially and up almost 33% yoy. This is the 6 straight month that TSMC has posted revenue of over NT$100billion.

Number 2 Taiwanese foundry UMC also had a good month recording revenue of US$4.67million for January up 19.5% yoy, and up 5% sequentially. UMC has also announced it will invest US$500million to expand capacity in its Chinese Xiamen 12inch Fab to boost capacity to 250k/month by mid 2021.

Specialist foundry Vanguard (VIS) was down though with the revenue dropping 8.9% sequentially to US$79million, and down 7.2% yoy. This was due to lower shipments over the Chinese New Year period.

Assembly and Test subcon ASE Technology holdings which includes both ASE and SPIL subcon groups reported monthly revenue for it’s ATM business of US$730million, which was down 5% sequentially but up 20.7% yoy.

Applied Materials, the market leader semiconductor equipment manufacturer gave an optimistic outlook for the semiconductor industry indicating companies are planning to spend more on capex in 2020. Applied Materials reported quarterly revenue for fiscal Q1, which ended Jan 26th, of US$4.16billion, up 11% yoy, the first increase in 5 quarters. They are forecasting US$4.34billion for fiscal Q2, which is up 22.6% yoy. They forecast minimal overall financial impact of COVID-19 virus for fiscal 2020, but do expect some changes in timings of revenues due to travel and logistics restrictions. Applied also said they were making good progress on regulatory approval for their acquisition of Kokusai Electric.

Austrian Sensor manufacturer AMS is pushing ahead with it’s plans to acquire Osram, and are pushing ahead to get what is known in Germany as a domination agreement to give AMS more control of Osram and to facilitate integrations efforts. AMS is asking Osram shareholders to approve the domination agreement which will require 75% approval at an EGM, the date of which is yet to be set.

ICInsights has published it’s latest report on worldwide Fab capacity, reporting that the top 5 semiconductor companies now supply 53% of global wafer capacity. The top 5 foundries are placed in the top 12, provide 24% of the worldwide capacity. Samsung with it’s large memory business holds the largest share with 15% of worldwide capacity, with TSMC 2nd with 12.8% and Micron 3rd with 9.4%. SK Hynix and Kioxia (formerly Toshiba Memory) making up the top 5 spots. It is interesting to note that 10years ago the top 5 companies only held 36% of the worldwide capacity showing how the industry is consolidating.

Qualcomm’s appeal against FTC’s antitrust victory against it was being heard in court last week in San Francisco. The judge stated that “Anticompetitive behaviour is prohibited under the Sherman Act. Hyper-competitive behaviour is not. This case asks us to draw the line between the two”

This week Samsung launched it’s next generation flagship phone which will be called Galaxy S20 and will have a 5G option and up to 4 cameras. They are hoping that 5G will revive demand for smartphones. Samsung also launch it’s next generation foldable phone the Galaxy Z Flip.

Photonics is one of the biggest growth areas in the IC market with a CAGR of over 20%. In 2013 the photonics IC market was 190million, this grew to 539million by 2017 and is expected to be between 1.3billion and 1.8billion by 2022, so the photonics market outlook is very bright.

Finally some sobering news and food for thought...

It is forecast that by 2030 there will be 20million manufacturing job layoffs due to robots powered by AI, big data and VR as Industry4.0 changes the way we live. In such an environment continued education and learning becomes essential. For the time being engineers are needed to create all these technologies, and the areas where most engineers will be needed will be AI & automation, Big Data, Generative Design and Digital Twins, Green Technology, VR/AR, robotics and 3D printing.
                    [post_title] => The Tech week that was February 10-14 2020
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                    [post_content] => Coronavirus Light SemiWiki 1Very solid quarter driven by foundry/logic
AMAT reported a very solid quarter, beating the top end of guidance with foundry and logic being the primary drivers of spend. Revenues were $4.16B and EPS of $0.98 non-GAAP versus street of $4.11B and $0.93 EPS.

Guide not too wide... - $300M "Corona Cut"
More importantly, given the Corona scare, guidance is for revenues of $4.34b +-$200M and EPS of $1.04 +- $0.06 versus current street of $4.02 and EPS of $0.92.

Management said that revenue outlook would have been $300M better if not taking a haircut due to Corona impact on chips. Management also commented that fiscal 2020 would not be negatively impacted by Corona as it views it as a temporary issue.

2020 WFE outlook of up 10-15% over 2019 - emphasis on 15%
Applied Managment pegged 2018 WFE spend at $56B with a 10-12% drop in 2019 (meaning $49B-$51B) and looking at a 10-15% increase expected in 2020 with a bias towards the high end of 15% which probably translates to a number just shy of $60B.

In our view this has a higher litho component as compared to 2018 and 2019 but dep & etch will obviously be up nicely as well.

The company added that they expect the $6.5B of spending that was China to be up another $2-$3B in spite of the Corona crisis as China continues to accelerate.

Flat panel to be Flat
Its probably not a surprise but flat panel equipment looks to be flat in 2020 overall as we don't have the 5G and memory recovery drivers that we have on the semi side.

We would expect flat panel to remain sluggish for a while without any new drivers of demand on the horizon.

NAND recovering , DRAM recovery is still a hope & prayer
As we have been saying for a while, NAND continues its slow recovery. AMAT management pointed out that inventories are down by half from their prior peak of 10-12 weeks with pricing also seeing a similar improvement.  DRAM is seeing no such recovery but everybody seems to be hopeful it will follow NANDs lead but there is zero evidence of things getting better in DRAM

A shallower cycle seems to be re-rating industry PE's
Applied was quick to point out that the peak to trough drop of this most recent downcycle was only 17% versus over 40% peak to trough variations in prior cycles and nearly 100% variation in older cycles.

While Applied management (and some inexperienced analysts) were obviously wrong in prior suggestions, a year or two ago, that the industry was no longer cyclical, we think they are more accurate in walking that back to the new statement that the cycles are now not as bad as they used to be and thus the PE's should be adjusted to reflect a less cyclical/more growth industry rather than the historical growth cyclical where growth premiums were canceled out by cyclical discounts to equal a market weight PE.

Overall industry PE's have obviously grown over the last several quarters as investors realize the cyclicality isn't as bad as the stocks were discounting.

We think this "re-rating" of PE's appears to have "stuck" as valuations continue to hold up at record levels despite the Corona risk in the stocks.

Trade war risk swapped out for Corona risk
We find it also interesting to note that the trade war risk with China has been replaced seemingly overnight with the Corona risk which doesn't seem to be having as bad an impact even though business is clearly slowing on the ground, as compared to the trade war risk which never actually impacted business.

We have heard many reports of machines not shipping or not being installed. Travel has ground to a halt in some areas.

Our view is that if Applied gets away with only a $300M haircut from Corona, in the quarter, they should count themselves as lucky.

Our view continues to be that the Corona risk, while temporary, will likely be worse than expected as the hysteria continues to grow.

The stocks
Obviously Applied stock will see nice upside from the nice quarter, great guide and minimal impact from Corona. 2020 outlook is bright and there appear to be no new potholes.  The Kokusai acquisition appears on track and will add more revenues even though its not at all strategic, which will add to the "growth" story.

We find it hard to chase some of these stocks at these record levels, which are "priced to perfection" in an imperfect market. The re-rating of PE's has clearly helped and stuck which is a good thing as we need a lot of support at these levels.
                    [post_title] => Minimal Corona Impact on Chip Equipment Stocks
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                    [post_content] => Stephen Crosher SemiWikiShall I compare thee to a…Rolls Royce jet engine?

‘There is a new era dawning whereby deeply embedded sensing within all technology will bring about great benefit for the reliability and performance of semiconductor-based products.’  These were my words during a presentation to an industry audience in China back in September 2015. During that same presentation, somewhat to the consternation of the technology veterans in the room, I also drew comparisons between semiconductor design and an aspect of aviation technology being offered by Rolls Royce. Why on earth would I do that?

I could envision real-time, high accuracy, embedded monitoring becoming ubiquitous in all technology. Plus, understanding that valuable insights can be gained from gathering large amounts of data across entire product ranges could enable a revolution within the semiconductor industry.

To explain my comparison for a moment –  A core principle of Rolls Royce’s R2 Labs Intelligent Engine is ‘data to insight.’ The technology offered by the aviation giant involves gathering mechanical, electronic and system level data for each jet engine in operation, wherever that may be in the world. Through centralised, large data analysis, Rolls Royce have enabled the ability to predict reliability issues, schedule engine maintenance and also allow for trends across fleets of aircraft to be assessed. My point back in Sept 2015 was, in the near future we shall be applying the same approaches and analytics principles to semiconductor devices. This ‘near future’ has now become our reality.

Gathering information from the physical world and acting upon it has been fundamental to human evolution.

In the modern day, how does this correlation to jet engines relate to semiconductors? The answer is within some of the challenges we can identify today – there is undeniable value in: predicting the failure of a critical automotive chip; or finding the operational sweet spot for a processor in terms of clock speed or power, steering an entire product range of data center chips to consume less power while achieving operational performance, such that carbon footprints are reduced by a power station or two.

I’m not the first to make comments of benefits of having an enlightened position through deeper observation. In 1665, Robert Hooke’s book ‘Micrographia’, (the first scientific best-selling book!) provides us with a good example the discovery of ‘Minute Bodies,’ or cells, through the use of magnifying glasses.

‘If you can’t measure it, you can’t improve it’ 

The famous management consultant Peter Drucker points out that, “If you can’t measure it, you can’t improve it.” A personal favourite is the inspired observation from Beyoncé, “You try and fix something, but you can’t fix what you can’t see.” I am sure that big data and a desire to seek patterns within dynamic semiconductor device behaviours was at the forefront of her mind as she wrote those lyrics!

Embedded monitoring within semiconductor devices will evolve, bringing with it a greater opportunity to consume less power, increase speed performance, enhance reliability and reduce design re-spin costs.  As technology evolves, as with my earlier jet engine analogy, expectations upon the semiconductor industry will increase from our vertical-market masters.

Today, solutions are available that will monitor the rapidly changing conditions within a chip, alongside assessments of how it has been fabricated, looking at variation from one chip to the next. This is all for the benefit of developing stable, reliable and optimized products. So my message to chip designers is that your chip is always saying something …. the question is are you listening?

https://moortec.com/blog/
                    [post_title] => The Future Of Embedded Monitoring - February 2020
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                    [post_content] => SLiC Library tool dramatically accelerates DTCO for 3nm and beyond

In advanced technology nodes below 10nm, Design and Process Technology development have become increasingly intertwined. In older nodes the traditional technology roll-out was done mostly in a sequential manner with clear geometry scaling targets set by process technology and then handed down to designers, determining the resulting scaling of area, power and performance.

This is no longer the case: Nowadays and going forward there are too many choices to be made between different materials, different patterning options, different device structures and different library architectures. The impact of each combination of variables and choices on design capabilities and performance is impossible to intuitively estimate or quantify.

In addition, the DTCO analysis needs to go beyond the device or library level. For example, a seemingly tighter library can prove to be very hard to place and route, causing routing congestion that would make it effectively much worse than a more relaxed library architecture. Effective DTCO today requires a feedback loop and negotiations between technology and design, and the assessment loop encompasses the entire flow: from technology capabilities and limitations, to logic cells, to placement and routing and analysis at the block level, and back.

DTCO Fig1 SPIE2020 Semiwiki

As seen in the above diagram, the centerpiece of this flow is the standard cell library. Developing a DTCO flow requires having a representative compact logic library that has frequently used logic building blocks (usually less than 200 cells would do). To accomplish an effective and streamlined flow one needs to be able to quickly create variants of this library and use them to implement a few logic designs or blocks that are characteristic to the specific target markets and product applications. Each implementation is analyzed for performance, power, area and cost (PPAC) and is evaluated against other technology and library architecture variants.

DTCO flow bottleneck and the SLiC solution
The DTCO flow must be quick and streamlined to evaluate multiple technology and architecture choices in a reasonable time. Most of the steps (e.g. synthesis, P&R) are automated but creating the library has been the bottleneck of this flow until recently. This critical gap has now been filled by SLiC (Standard-cell Library Compiler), a new tool that solves this problem by automating library creation and cutting the library physical design time from months to less than a day. SLiC has been recently introduced by Sage Design Automation and has proven extremely efficient, creating libraries very quickly with optimal results that are as good and sometimes better than handcrafted.

Unlike past generations of library creation or migration tools, setting up each new technology for SLiC takes less than a day and the run time is measured in hours. SLiC was designed from the ground up for new and advanced technologies. Its inherent versatility accommodates novel devices and logic design concepts including LGAA, CFETs and even more exotic 3D structures and cell architectures.  SLiC has already been used and proven in both DTCO and production flows for 7nm, 5nm, 4nm technologies and 3nm pathfinding DTCO work.

DTCO Fig2 SPIE2020 SemiWiki

Summary
Standard cell libraries are at the center of the process technology and design development for advanced nodes. SLiC enables very quick creation of optimal quality libraries that can be used both for production in advanced nodes and for pathfinding DTCO of future technologies.

Come and see SLiC at SPIE:   SLiC will be presented at the SAGE-DA booth #103 on the exhibit floor at the 2020 SPIE Advanced Lithography Conference in San Jose (Feb 25th-26th). You are also encouraged to attend the paper “DTCO acceleration to fight scaling stagnation” (Paper 11328-11), showing advanced DTCO work done using SLiC.

https://www.sage-da.com
                    [post_title] => Design Technology CoOptimization at SPIE 2020
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                    [post_content] => In a rare and perhaps unfortunate moment of candor, Cruise Automation CEO Dan Ammann wrote, in his blog post describing the emergence of Cruise (a subsidiary of General Motors) that conventional internal combustion engine vehicles “break down relatively easily. And if they make it 150,000 miles, well, lucky you.”

Ammann goes on to say: “The Cruise Origin (electric autonomous shuttle due for mass production in 2022)… will have a lifespan of over 1 million miles — six times more than the average car.”

There’s just one problem with this quote. Ammann is speaking on behalf of a division of General Motors, which itself makes millions of those lucky-if-you-make-150,000-mile cars. As consumers become increasingly aware of the virtues of EV ownership, life may become very difficult for the sellers of ICE's - dealers and car makers alike. Just ask your friendly neighborhood fleet operator. Most of them have already seen the future and put their money on battery electric vehicles.

Ammann is onto something many other consumers and researchers already know. Fleet operators around the world fielding Tesla’s or even hybrids like the Toyota Prius are routinely seeing multiple-hundred-thousand-mile performance. The longevity of electric powertrains is reality, not theory.

Battery electric vehicles have fewer moving parts. They require less service and they last longer.

Now AAA has gotten on board with a study identifying the higher operating costs – for fuel and service – of ICE vehicles vs. EVs, publishing a study on the subject. The annual savings amount to 2-3 monthly payments - about $950. AAA's consumer insights show growing interest in EV ownership.

AAA Study results

These findings validate analysis from Kelly Blue Book and Vincentric pointing to the lower cost of operation for EVs, particularly those that see the highest rates of usage. The more you drive them, the longer they last – or so it seems.
[caption id="attachment_282342" align="alignnone" width="733"]Savings Tip the Balance to EVs SOURCE: Vincentric[/caption]
This phenomenon has not been lost on car sharing and ride hailing operators, and rental car companies which are rapidly shifting to electric powertrains. Makers of ICE vehicles may “perceive” consumer resistance due to range anxiety, the limited availability of charging stations, or sticker shock – but they are slowly discovering the groundswell of consumer interest which will soon be fed by a gusher of new electric vehicles – more than 180, to be exact, coming in the next few years, according to a report from car share operator Vulog. Access Vulog report With or without incentives, with or without unlimited range, with or without sufficient charging stations, EVs are transforming the automotive landscape – beginning with Tesla and through the growing demand from fleet operators – including car sharers. According to the Vulog report, 17 major cities around the world will ban ICE vehicles by 2025 or 2030. More than a dozen countries have set ICE production/sales cutoff dates of 2040 or sooner. LMC Automotive published a blog post today noting the potential for the automotive industry to have hit what it calls “Peak Auto.” The company attributes the arrival at this turning point to uncertain demand in markets where some of the most rapid growth had previously occurred – such as India, China, Brazil, and other emerging markets - along with tepid sales in mature markets. LMC Automotive "Peak Auto" blog LMC has a point. But there is a more chilling reality setting in. The reality is that there are consumers looking at the ICE vehicles in their driveways, garages, and parking lots and thinking: "That is the last ICE vehicle I will ever buy." And when those consumers start buying their million-mile electric vehicles, they may not return to a new car dealer lot for a very long time. [post_title] => Savings Tip the Balance to EVs [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => savings-tip-the-balance-to-evs [to_ping] => [pinged] => [post_modified] => 2020-02-13 09:17:21 [post_modified_gmt] => 2020-02-13 17:17:21 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=282341 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 1 [filter] => raw ) [7] => WP_Post Object ( [ID] => 282526 [post_author] => 16 [post_date] => 2020-02-13 06:00:45 [post_date_gmt] => 2020-02-13 14:00:45 [post_content] => I wrote recently on ANSYS and TSMC’s joint work on thermal reliability workflows, as these become much more important in advanced processes and packaging. Xilinx provided their own perspective on thermal reliability analysis for their unquestionably large systems – SoC, memory, SERDES and high-speed I/O – stacked within a package. This was presented at the ANSYS Innovation Conference in Santa Clara recently. They put special emphasis on applications on datacenters and automotive, two areas where FPGAs are playing important roles for their ability field-upgradable to meet new demands. thermometer I’ve talked before about AI functions in the datacenter. Die sizes of leading-edge 7nm AI chips are already reaching reticle limits and consume hundreds of watts of power. Automotive electronics, on the other hand, operate in very harsh environments for extended periods of time. They must be highly reliable, safe and have a zero-field failure rate over a life span of 10 to 15 years. The smallest failure in a safety critical system could potentially cause a fatality, which is unacceptable. Both create new demands to ensure thermal reliability. Thermal reliability is a big deal in these advanced designs for multiple reasons. First FinFET transistors are prone to something called self-heating. They heat up more quickly than traditional planar transistors. Second, interconnects have some resistance and generate heat when current flows (Joule heating). Third, heat dissipates very slowly on electronic switching time scales. And fourth, all this heating is compounded when you stack chips on top of each other. That’s a problem for reliability because increased temperatures affect (among other things) increased electromigration (EM), thermally induced mechanical stress and solder joint fatigue, leading ultimately to functional failures. Thermal aware EM flow What I found interesting about the Xilinx story, because I’m a math and physics nerd, is that Xilinx and ANSYS shared a bit more on how this flow handles modeling for the heat diffusion problem in chip/package structures. ANSYS RedHawk (or ANSYS Totem for analog blocks) computes, based on detailed knowledge of layout and structures together with simulation, a T (temperature above nominal) for each wire. This comes from self-heating and Joule-heating. Do this for all wires. Then, per wire, look at the impact of heating in neighboring wires. The closer a neighbor is to the wire of interest, the higher the impact it will have. These coupling contributions are calibrated to the process in the tool. Add together all meaningful contributions from neighboring wires (superposition) and you get the total heating in the current wire. Turns out this can overestimate heating in some cases. For example, foundry estimates might show no more than a 5o T in areas of dense heating, where a superposition calculation can exceed that limit. Xilinx and ANSYS figured out a way to compensate for this effect by applying a T clamping approach which bounds this over-estimate. It also estimates heating for current flow isolated to a single wire to more like 1.25o, well below the nominal 5o T, correlating well with foundry estimates. Based on these calculations, local EM failure rates can be calculated quite accurately and can show, especially in those isolated wire heating instances, less pessimistic estimates than global approaches. Xilinx next talked about temperature gradients across the chip. Traditionally you require that worst-case transistor junction temperatures be held below some maximum allowable level across the design. Heating from any of the above sources adds to this problem, leaving you with few options – spread out any places that get hot, wasting area or go for a bigger device, or run the clock slower until the chip cools down. But a more granular approach may show that trying to design your way out of the problem is over-compensating. Here the Xilinx approach gets interesting. They calculate a cumulative failure rate (CFR) for the chip in a composition fashion, where each block has its own CFR budget. For blocks where T is low in this temperature distribution, there is no concern. For a block where T is high, they re-examine the CFR budget for that block to determine if it can be adjusted to still ensure an acceptable lifetime for the whole device. They don’t explain how they do this, but they do provide a couple of references that the more determined among you may find relevant. Interesting study, you can learn more by registering to watch the webinar. [post_title] => Thermal Reliability Challenges in Automotive and Data Center Applications – A Xilinx Perspective [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => thermal-reliability-challenges-in-automotive-and-data-center-applications-a-xilinx-perspective [to_ping] => [pinged] => [post_modified] => 2020-02-09 14:54:11 [post_modified_gmt] => 2020-02-09 22:54:11 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=282526 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 3 [filter] => raw ) [8] => WP_Post Object ( [ID] => 282766 [post_author] => 13 [post_date] => 2020-02-12 10:00:52 [post_date_gmt] => 2020-02-12 18:00:52 [post_content] => Machine Learning (ML) has become extremely important for many computing applications, especially ones that involve interacting with the physical world. Along with this trend has come the development of many specialized ML processors for cloud and mobile applications. These chips work fine in the cloud or even in cars or phones, but they are nowhere miserly enough when it comes to power consumption for use in IoT applications. For instance, many automotive ML processors use between 100W and 500W. Edge devices such as phones can get by with one tenth of a watt, but to go into what Eta Compute calls the extreme edge, power consumption has to be in the realm of 1 to 10mW. Let’s look at some extreme edge applications and why it is useful to have ML processing performed locally. IoT devices at the extreme edge will perform many sensor related tasks. Examples are thermostats, occupancy sensors, smoke detectors, etc. Included in this group are medical and fitness devices such as fitness bands, health monitors and hearing aids. For commercial applications we see things like asset tracking, retail beacons and remote monitoring. Many of these use small batteries and require long battery life. Some even rely on energy harvesting for power. Looking at the list above it becomes clear how ML could be useful. Yet these devices cannot afford the energy budget to transfer raw data to the cloud for processing. There is also a cost saving to not relying on cloud processing for every IoT device that needs ML capabilities. Another benefit is the low latency achieved by saving a trip to the cloud for recognition tasks or even training. The solution is to build highly optimized ML processors for IoT and extreme edge usage. This is exactly what Eta Compute has done with its announcement of their ECM3532 Neural Sensor Processor at the second TinyML Summit held in San Jose on February 12th. The ECM3532 is an SoC for ML and can be trained with the popular. TimyML ECM3532 Architecture TensorFlow software. Their chip is especially interesting because it gains a huge efficiency advantage through their self-timed continuous voltage and frequency scaling (CVFS) technology. Because the control CPU and the DSP, which includes optimized MAC units, both use CVFS they are seeing a 10x reduction in power compared to traditional clocking and voltage supply approaches. The ECM3532 contains an ARM Cortex-M CPU and a dual MAC 16-bit DSP. It also has onboard memory (Flash, SRAM, ROM), an ADC, serial interfaces, GPIOs, RTC, clock generation and power control. Running a variety of different benchmarks and applications, the ECM3532 is able to perform inference with less than 1mA of power consumption. Even when running COREMARK at up to 100 MHz its power consumption stays in the single digit mW range. The chip is capable enough, with 512KB of Flash and 256KB SRAM, for Eta Compute to provide demos in speech, image and video recognition, and industrial sensors. To provide flexibility in communication choices, the ECM3532 itself does not have onboard RF support, but it is expected to be designed into packages or boards with any desired wireless protocol chip or chiplet for cloud connectivity. Because of their architecture choices on CPU, DSP and MAC, they are seeing excellent results in performance. On the CIFAR-10 CNN dataset they were able to reduce the number of operations required by a factor of 10 and reduce the weight size by 2 and achieve similar accuracy compared to published academic results. Eta Compute is opening the doors to making IoT devices smarter and more responsive without drawbacks of shorter battery life or infeasible unit costs. Smarter IoT devices will offer more functionality and play a larger role in industry, medicine, appliances and elsewhere. It will be interesting to see the applications that are developed using this breakthrough technology. More information on their announcement can be found on the Eta Compute website. [post_title] => TinyML Makes Big Impact in Edge AI Applications [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => tinyml-makes-big-impact-in-edge-ai-applications [to_ping] => [pinged] => [post_modified] => 2020-02-12 13:51:59 [post_modified_gmt] => 2020-02-12 21:51:59 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=282766 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [9] => WP_Post Object ( [ID] => 282402 [post_author] => 11830 [post_date] => 2020-02-12 06:00:12 [post_date_gmt] => 2020-02-12 14:00:12 [post_content] => At DesignCon 2020, ANSYS sponsored a series of very high-quality presentations.  Some focused on advanced methods and new technology exploration and some provided head-on, practical and actionable capabilities to improve advanced designs. The presentation I will discuss here falls into the latter category. The topic was presented by Anand Raman, senior director of application engineering for on-chip EM solutions at ANSYS. Anand is one of those people who has infectious enthusiasm.  He will draw you into whatever topic he is presenting and get you involved. Given the impact of his material, it was quite easy to do in this case. Anand began by pointing out that most people understand the need for electromagnetic (EM) analysis for high-frequency RF designs (chip and board). The structures and operating frequencies of this class of design utilize “purposeful inductance” that needs to be modeled. He then pointed out that these challenges can also exist in ultra-high-speed digital designs, in subtle and hard-to-find ways that can cause large problems due to parasitic inductance. A collection of correctly designed and verified blocks can fail when assembled onto a chip due to remote coupling effects. Power/ground networks can become channels to create these subtle problems. Anand pointed out that extremely thin routes that run long distances and carry very high-speed data is a formula for extreme inductance effects. Capacitance extraction has been widely used in digital design for a while now. It’s time to consider inductance effects as well. Parasitic inductance causes two problems – signal distortion and parasitic coupling due to the magnetic field. It turns out that an EM-aware design flow can do more than ensure a working chip. It can also provide the opportunity to improve circuit density as well. The figure below summarizes some of these effects for two generations of the same design. The second one is over 37% smaller, owing to the ongoing and complete modeling of all EM effects, allowing for a more aggressive design. EM-aware improvements in two generations of the same design Going back to the subtle and non-intuitive nature of magnetic coupling, Anand provided a good graphic to explain the problem, see below. The third loop mentioned below could be created by the thousands of structures in a power distribution network. Subtle and non-intuitive magnetic coupling ANSYS provides a platform of tools to get to the required level of coverage for a true EM-aware design flow. These tools integrate with existing digital design flows and provide several levels of analysis support. The tools, and their field of application, are summarized below. ANSYS platform for EM-aware design Regarding the other benefits of an EM-aware design flow, several examples were presented based on real designs. In one case, shown below, active circuitry was folded under an inductor, resulting in substantial area savings. This was made possible by analysis from the previously mentioned ANSYS EM tool platform to ensure this change did not introduce EM coupling effects. VeloceRF was also used to synthesize a much smaller inductor.  Overall, there was a 66% area saving with slightly better performance. EM-aware design improvement Several other real design examples were presented that highlight the way subtle EM coupling can cause significant design problems. These examples included a working chip that degraded in the package due to EM crosstalk from the ground net to the first few package layers. Other cases of degradation due to coupling through the package were presented. Another interesting case illustrated how the seal ring in a chip cause an inductive coupling loop. I would say Anand made a strong and passionate case for the benefits of an EM-aware design flow. To check out an example of a customer case study on the topic of de-risking high-speed serial links from on-chip electromagnetic crosstalk and power distribution issues, click HERE. [post_title] => De-Risking High-Speed RF Designs from Electromagnetic Crosstalk Issue [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => de-risking-high-speed-rf-designs-from-electromagnetic-crosstalk-issue [to_ping] => [pinged] => [post_modified] => 2020-02-12 08:00:43 [post_modified_gmt] => 2020-02-12 16:00:43 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=282402 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) ) [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object ( [ID] => 282893 [post_author] => 27471 [post_date] => 2020-02-17 10:00:58 [post_date_gmt] => 2020-02-17 18:00:58 [post_content] => Central America and Mexico Tour SiFive SemiWiki We’re confirming seats for our first two SiFive Tech Symposiums in 2020. The first will take place in San José, Costa Rica on February 25, and the second will be in Mexico City, Mexico, on February 28. Just like our 2019 symposiums, these events are designed to engage the global hardware community in the RISC-V ecosystem, and to further promote the revolution that’s taking place within the semiconductor industry. We’re proud to have Western Digital is our co-host in Costa Rica, and the Computing Research Center at CIC-IPN is our co-host in Mexico. Both events will feature presentations on RISC-V development tools, platforms, core IP and SoC IP, as well as talks about the exciting opportunities stemming from RISC-V, and the leading-edge research taking place in academia. Both events will also include a hands-on workshop where attendees will have the opportunity to configure their own RISC-V core and bring up on an FPGA. Attendance is free, but registration is required. San José, Costa Rica Co-located with LASCAS 2020 Mexico City, Mexico Instituto Politécnico Nacional/National Polytechnic Institute of México The learn more about other SiFive Tech Symposiums taking place throughout the world in 2020, please visit the website, and check back often for updates. We look forward to seeing you soon! About RISC-V Foundation RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 500 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem. About SiFive SiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 14 offices worldwide, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, www.sifive.com.   [post_title] => The First SiFive Tech Symposiums of 2020 are Fast Approaching – We’ll be in San José, Costa Rica, and Mexico City This Month [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => the-first-sifive-tech-symposiums-of-2020-are-fast-approaching-well-be-in-san-jose-costa-rica-and-mexico-city-this-month [to_ping] => [pinged] => [post_modified] => 2020-02-17 07:59:43 [post_modified_gmt] => 2020-02-17 15:59:43 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=282893 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [comment_count] => 0 [current_comment] => -1 [found_posts] => 6864 [max_num_pages] => 687 [max_num_comment_pages] => 0 [is_single] => [is_preview] => [is_page] => [is_archive] => [is_date] => [is_year] => [is_month] => [is_day] => [is_time] => [is_author] => [is_category] => [is_tag] => [is_tax] => [is_search] => [is_feed] => [is_comment_feed] => [is_trackback] => [is_home] => 1 [is_privacy_policy] => [is_404] => [is_embed] => [is_paged] => 1 [is_admin] => [is_attachment] => [is_singular] => [is_robots] => [is_posts_page] => [is_post_type_archive] => [query_vars_hash:WP_Query:private] => be5e53b79b80fec6b5d4579b560cf847 [query_vars_changed:WP_Query:private] => [thumbnails_cached] => [stopwords:WP_Query:private] => [compat_fields:WP_Query:private] => Array ( [0] => query_vars_hash [1] => query_vars_changed ) [compat_methods:WP_Query:private] => Array ( [0] => init_query_flags [1] => parse_tax_query ) [tribe_is_event] => [tribe_is_multi_posttype] => [tribe_is_event_category] => [tribe_is_event_venue] => [tribe_is_event_organizer] => [tribe_is_event_query] => [tribe_is_past] => )

The First SiFive Tech Symposiums of 2020 are Fast Approaching – We’ll be in San José, Costa Rica, and Mexico City This Month

The First SiFive Tech Symposiums of 2020 are Fast Approaching – We’ll be in San José, Costa Rica, and Mexico City This Month
by Swamy Irrinki on 02-17-2020 at 10:00 am

Central America and Mexico Tour SiFive SemiWiki

We’re confirming seats for our first two SiFive Tech Symposiums in 2020. The first will take place in San José, Costa Rica on February 25, and the second will be in Mexico City, Mexico, on February 28. Just like our 2019 symposiums, these events are designed to engage the global hardware community in the RISC-V ecosystem, and to further… Read More


Mentor at DVCON 2020!

Mentor at DVCON 2020!
by Daniel Nenni on 02-17-2020 at 6:00 am

DVCon 2020 SemiWiki

Are you ready for the premier conference for functional design and verification of electronic systems?

Sponsored by Accellera Systems Initiative, DVCon is an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP)… Read More


The Tech week that was February 10-14 2020

The Tech week that was February 10-14 2020
by Mark Dyson on 02-16-2020 at 10:00 am

Semiconductor Weekly Summary 1

The new coronavirus outbreak or COVID-19 outbreak, as it is now officially called, continues to dominate the news again this week as currently there is no end forecast to the outbreak, and infection numbers continue to rise. This will have an impact on semiconductor supplies in the coming months and into Q2 as the necessary restrictions… Read More


Minimal Corona Impact on Chip Equipment Stocks

Minimal Corona Impact on Chip Equipment Stocks
by Robert Maire on 02-16-2020 at 6:00 am

Coronavirus Light SemiWiki

Very solid quarter driven by foundry/logic
AMAT reported a very solid quarter, beating the top end of guidance with foundry and logic being the primary drivers of spend. Revenues were $4.16B and EPS of $0.98 non-GAAP versus street of $4.11B and $0.93 EPS.

Guide not too wide… – $300M “Corona Cut”
More importantly,… Read More


The Future Of Embedded Monitoring – February 2020

The Future Of Embedded Monitoring – February 2020
by Stephen Crosher on 02-14-2020 at 10:00 am

Stephen Crosher SemiWiki

Shall I compare thee to a…Rolls Royce jet engine?

‘There is a new era dawning whereby deeply embedded sensing within all technology will bring about great benefit for the reliability and performance of semiconductor-based products.’  These were my words during a presentation to an industry audience in China back in SeptemberRead More


Design Technology CoOptimization at SPIE 2020

Design Technology CoOptimization at SPIE 2020
by Daniel Nenni on 02-14-2020 at 6:00 am

DTCO Fig1 SPIE2020 Semiwiki

SLiC Library tool dramatically accelerates DTCO for 3nm and beyond

In advanced technology nodes below 10nm, Design and Process Technology development have become increasingly intertwined. In older nodes the traditional technology roll-out was done mostly in a sequential manner with clear geometry scaling targets set by … Read More


Savings Tip the Balance to EVs

Savings Tip the Balance to EVs
by Roger C. Lanctot on 02-13-2020 at 10:00 am

Savings Tip the Balance to EVs

In a rare and perhaps unfortunate moment of candor, Cruise Automation CEO Dan Ammann wrote, in his blog post describing the emergence of Cruise (a subsidiary of General Motors) that conventional internal combustion engine vehicles “break down relatively easily. And if they make it 150,000 miles, well, lucky you.”

Ammann goes… Read More


Thermal Reliability Challenges in Automotive and Data Center Applications – A Xilinx Perspective

Thermal Reliability Challenges in Automotive and Data Center Applications – A Xilinx Perspective
by Bernard Murphy on 02-13-2020 at 6:00 am

thermometer

I wrote recently on ANSYS and TSMC’s joint work on thermal reliability workflows, as these become much more important in advanced processes and packaging. Xilinx provided their own perspective on thermal reliability analysis for their unquestionably large systems – SoC, memory, SERDES and high-speed I/O – stacked within a … Read More


TinyML Makes Big Impact in Edge AI Applications

TinyML Makes Big Impact in Edge AI Applications
by Tom Simon on 02-12-2020 at 10:00 am

TimyML ECM3532 Architecture

Machine Learning (ML) has become extremely important for many computing applications, especially ones that involve interacting with the physical world. Along with this trend has come the development of many specialized ML processors for cloud and mobile applications. These chips work fine in the cloud or even in cars or phones,… Read More


De-Risking High-Speed RF Designs from Electromagnetic Crosstalk Issue

De-Risking High-Speed RF Designs from Electromagnetic Crosstalk Issue
by Mike Gianfagna on 02-12-2020 at 6:00 am

Picture3 1

At DesignCon 2020, ANSYS sponsored a series of very high-quality presentations.  Some focused on advanced methods and new technology exploration and some provided head-on, practical and actionable capabilities to improve advanced designs. The presentation I will discuss here falls into the latter category. The topic was… Read More