SRAM compilers targeting automotive SoCs on advanced nodes

Processor IP garners the most attention in SoC design, but it’s not the only IP category begging for smart choices. Every processor core needs to be fed with data; however, frequent off-chip DRAM access incurs a large clock-cycle penalty each time. Architects now want SRAM blocks distributed throughout an SoC, putting data close to where it is used and minimizing moves. With all this on-chip memory, advanced SRAM compilers can differentiate automotive SoCs, especially those implementing AI, which demand performance and reliability. A Synopsys white paper details the benefits of its SRAM compilers targeting automotive SoCs on 5nm and 3nm process nodes, describing the trends, challenges, and solutions.

More SRAM blocks are good, but too many can worsen automotive reliability

In traditional Von Neumann processor architectures, the solution to data latency has been cache memory, with up to three levels in large CPU-centric designs. A well-designed cache can prevent critical, frequently used data from facing competition for bandwidth on an already overcrowded bus. However, Von Neumann never met an AI application. AI models of more than trivial complexity don’t lend themselves to caching, with unique incoming frames of streaming data and unpredictable, potentially vast intermediate result sets as data sift through layers of weighting and summation.

For that matter, Von Neumann never met a car filled with electronic content, either. Automotive electronics are transforming. The traditional domain-based approach, in which a controller chip handles a specific function or a small set of functions, remains in use. A newer architecture is gaining momentum: zonal controllers, which are responsible for operations within a specific section of the car. In theory, zonal architectures can reduce wiring harness complexity and cost. However, zonal SoC complexity can increase, with combinations of CPUs, GPUs, I/O blocks, and, to handle AI tasks, neural processing units (NPUs).

Both domain-based and zonal architectures are pushing designers to adopt distributed SRAM within an SoC to simplify routing and bring data closer to the points of computation, enabling greater throughput. Distributing SRAM is crucial for AI implementations, where constantly moving intermediate results too far across a chip can become a performance bottleneck. Placing smaller SRAM chunks closer to small groups of multiply-accumulate units in AI accelerators, or polygon-processing cores in GPUs, improves performance.

According to Synopsys’ white paper, an advanced automotive SoC might have up to 50% of its area occupied by embedded SRAM, often with some concentrated and some distributed in smaller blocks. These sheer amounts of SRAM make power, performance, and area (PPA) optimization a high priority. Another side effect of large amounts of SRAM operating in harsh environmental conditions with relatively long target life is that defective parts per million (DPPM) standards quickly come into play, far more than in consumer electronics design.

Aggressive process nodes require sophisticated SRAM compilers

Another important trend in automotive SoCs is moving to more aggressive process nodes to handle increasing complexity, particularly in zonal architectures, but also applicable to domain-based architectures. TSMC offers its N5A process tuned for automotive needs at 5nm, and the latest N3A automotive process at 3nm for even higher automotive computational loads, including AI inference. These are advanced nodes just behind cutting-edge processes for benign-environment SoCs, with appropriate steps to help designers achieve automotive-level reliability and functional safety (FuSa) requirements while meeting PPA goals.

Synopsys supports both TSMC N5A and N3A automotive processes, with a portfolio of SRAM compilers that offer a wide array of memory functions. Which compiler(s) designers choose for an automotive project depends on specific goals, falling into several categories:

• High-speed compilers using high-current bit cells for maximum performance
• Ultra-high-density compilers using small-area, low-power bit cells
• High-density compilers optimized for medium speed and power efficiency
• Pseudo two-port architectures for further power and area reduction

Their white paper launches into a discussion of using these SRAM compilers to reduce leakage and dynamic power, using techniques such as dynamic voltage and frequency scaling (DVFS). Lower power directly translates to lower thermal dissipation and a corresponding improvement in long-term reliability. There are also customer stories, including one showing how eliminating a performance bottleneck through timing improvements achieved higher SRAM clock rates, and two that show improvements across all three dimensions of PPA.

Also in the white paper are specific steps to address ultra-low DPPM requirements with SRAM in TSMC N5A and N3A, and how Synopsys memory compilers provide an ASIL-D-ready solution for ISO 26262 certification. It’s a concise discussion with an encouraging message: design teams can move to advanced process nodes with confidence and use SRAM compilers to solve PPA issues they are likely to encounter in higher-complexity automotive SoC designs. To learn more, download the Synopsys white paper:

Accelerating Automotive Innovation: SRAM Compiler Breakthroughs for 5nm and 3nm SoCs