Synopsys and Intel Foundry Enable System-Level Design on Intel 14A

Synopsys and Intel Foundry are expanding their collaboration to accelerate customer adoption of Intel 14A, connecting advanced process technology with production-ready electronic design automation, silicon intellectual property, multiphysics analysis, and multi-die integration. Announced at the 2026 DAC Chips to Systems Conference, the collaboration moves beyond conventional process enablement toward system-aware co-design. Its objective is to help developers translate angstrom-scale innovation into predictable power, performance, area, reliability, and time-to-tapeout outcomes for artificial intelligence and high-performance computing systems.

Intel 14A builds on the architectural foundation established by Intel 18A. The process introduces RibbonFET 2, Intel’s second-generation gate-all-around transistor architecture, and PowerDirect, an advanced backside power-delivery technology. PowerDirect extends the principles of PowerVia by delivering power more directly to transistors, separating critical power and signal resources and supporting greater routing efficiency. Intel also introduces double-height Turbo Cells for performance-critical paths, enabling designers to selectively increase drive current and frequency without applying high-power cells across an entire block. Intel projects that 14A will deliver a 15–20% performance-per-watt improvement at equal power, a 25–35% power reduction at equal performance, and up to 30% greater chip density compared with Intel 18A. These projections remain workload- and implementation-dependent. (Intel Foundry)

Realizing those process benefits requires design tools that understand the interaction among devices, interconnects, power networks, packaging, and workloads. Synopsys has certified AI-powered implementation and signoff flows for Intel 14A, extending collaboration from design-technology co-optimization into system-aware co-optimization. The flows use AI-assisted exploration to evaluate implementation alternatives and improve convergence against PPA objectives. By encoding Intel 14A design rules, extraction models, timing behavior, and manufacturing constraints within familiar Synopsys environments, the collaboration reduces the effort required to introduce the process into established development methodologies.

Multiphysics analysis is especially important because backside power delivery and dense heterogeneous integration make electrical, thermal, and mechanical behavior increasingly interdependent. Synopsys combines implementation and signoff with power-integrity, thermal, and electromagnetic analysis. Engineers can therefore identify voltage drop, current-density limits, thermal gradients, signal-integrity degradation, and package interactions before tapeout. Earlier visibility helps prevent a local optimization—such as denser placement or higher-frequency operation—from creating an unacceptable thermal or power-delivery condition elsewhere in the system. This integrated methodology is intended to reduce late-stage redesign and improve the probability of first-pass silicon success.

The collaboration also addresses the transition from monolithic systems-on-chip to multi-die architectures. Synopsys 3DIC Compiler provides an exploration-to-signoff environment for designs using Intel Embedded Multi-die Interconnect Bridge and EMIB-T packaging. Supported capabilities include early bump and through-silicon-via planning, automated Universal Chiplet Interconnect Express and high-bandwidth-memory routing, and analysis spanning dies, bridges, package structures, and power-delivery networks. Designers can optimize signal integrity, thermal behavior, and power integrity concurrently instead of treating package implementation as a downstream activity. This approach is valuable for AI accelerators, where compute tiles, HBM stacks, high-speed I/O, and specialized chiplets must operate as a single power- and bandwidth-constrained system.

Customer readiness is further strengthened by Synopsys interface and foundation IP optimized for Intel 14A. The planned portfolio includes PCI Express 7.0, 224-gigabit-per-second SerDes, USB4, and embedded USB, together with embedded memories, standard-cell libraries, and I/O libraries. Pre-designed and process-optimized IP can shorten subsystem development, reduce interface verification risk, and allow engineering teams to concentrate resources on differentiated compute architectures. (Synopsys)

Bottom line: The work creates a silicon-to-systems enablement path rather than a collection of isolated tools. Intel supplies the process, packaging technologies, manufacturing infrastructure, and process-design-kit foundation; Synopsys supplies certified EDA flows, system analysis, multi-die design capabilities, and reusable IP. The result is earlier architectural feedback, more predictable design closure, reduced integration risk, and a faster route from an Intel 14A concept to a manufacturable AI or HPC system.

Press Release.

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