AI Memory Gap at DAC 2026

On Tuesday at #DAC2026 I attended the exhibitor presentation, Synopsys: How Silicon Startups are Addressing the AI Memory Gap. Vikram Bhatia from Synopsys introduced the two presentations from Wenbo Yin, SVP of IC Design at TetraMem and R. Scott Hills, VP of Business Development at ANAFLASH. Datacenters consume large amounts of HBM chips in their AI hardware systems, but these two companies are taking a different approach by computing directly inside non-volatile memory, avoiding the power-hungry step of moving data between memory and processor.

Wenbo from TetraMem was first to present and his company started in 2018, with their first multi-level ReRAM chip for In Memory Compute (IMC) shipping in 2026, protected by over 120 patents. There are already over 10 silicon tape-outs so far using their IMC. The classic multiply-accumulate step happens inside the RRAM array, avoiding the high bandwidth IO bottleneck altogether.

The AI weights are programmed right into the array, creating instant, high-throughput MAC. Using multi-level resistive random-access memory (RRAM) allows precision programming with up to 11 bit/cell, making for a smaller area and power compared to digital memory. This crossbar technology is also scalable to advanced nodes.

An example chip called the MLX200 used a 22nm process for Edge-AI acceleration, which had a RISC-V CPU coupled with an analog IMC NPU macro, along with integrated audio and peripheral blocks. The market for this chip is wearable health that uses voice and detection, always-on wake, and keyword spotting features.

TetraMem used Synopsys Cloud in their workflow to provide quick system bring-up in just minutes, avoid unexpected down time, experience little maintenance time, and speed Register Transfer Level (RTL) verification simulation, all without additional CAD engineers and IT infrastructure resources.

ANAFLASH presented next with Mr. Hills first talking about their Reflex Computing Unit that mimics the behavior of sensory neurons and motor neurons by using nonvolatile AI computing technology coupled with FLASH memory. This approach eliminates AI model traffic.

The second chip from ANAFLASH is a time-domain Neural Network Processor, dubbed Legato-Logic, that eliminates excessive data traffic, allowing for a low-power and low-latency execution of large AI models right where they are stored. Legato-Logic uses standard logic and a time-domain compute-in-memory technology that integrates into any type of memory, reducing data traffic between processor and memory.

Challenges at ANAFLASH were resource constraints under the product development schedule, a global design team, and the desire to use well-established IP. The Synopsys Cloud offering fit their requirements quite well.

Summary

I was impressed with the in-memory approaches that these two companies delivered to the market for edge AI cases. There are many commercial uses where always-on capabilities and low-power efficiency dominate the requirements, and both TetraMem and ANAFLASH have proven that their chips fit those needs. These companies also used Synopsys Cloud to get their products to market without their design teams needing to hire extra CAD and IT engineers to support an EDA infrastructure.

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