Application-Specific Lithography: 5nm Node Gate Patterning

Application-Specific Lithography: 5nm Node Gate Patterning
by Fred Chen on 09-08-2022 at 6:00 am

Blur Limitations for EUV Exposure

It has recently been revealed that the N5 node from TSMC has a minimum gate pitch of 51 nm [1,2] with a channel length as small as 6 nm [2]. Such a tight channel length entails tight CD control in the patterning process, well under 0.5 nm. What are the possible lithography scenarios?

Blur Limitations for EUV Exposure

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