Panel Discission: Beyond Moore’s Law and the Future of Semiconductor Manufacturing

The semiconductor industry is entering a post-Moore’s Law era in which scaling transistor density alone is no longer sufficient to sustain historical performance growth. As discussed in the panel Beyond Moore’s Law: The Future of Semiconductor Manufacturing, the industry is increasingly dependent on advanced manufacturing intelligence, heterogeneous integration, AI-driven optimization, and data-centric infrastructure to continue innovation. Rather than relying solely on lithographic shrink, semiconductor progress is now driven by system-level efficiency, packaging technologies, and intelligent manufacturing ecosystems.

Panelists:

• Dr. Jim Shiely, Director, R&D Calibre Semi Manufacturing, Siemens EDA
• Dr. Larry Melvin, Sr. Director, Technical Product Management, Synopsys
• Dr. Christophe Begue, VP, Corporate Strategic Marketing, PDF Solutions
• Dr. Janhavi Giri, EDA & Semiconductor Industry Vertical Lead, NetApp
• Daniel Nenni, Founder of SemiWiki.com  (Moderator)

One of the primary technical challenges highlighted is the physical limitation of traditional CMOS scaling. As transistor geometries approach atomic dimensions, issues such as leakage current, thermal dissipation, quantum tunneling, and variability become increasingly difficult to control. Advanced nodes below 3 nm require extreme ultraviolet (EUV) lithography, multi-patterning, and highly precise process controls, significantly increasing manufacturing complexity and cost. Consequently, fabs generate enormous volumes of operational data from process equipment, metrology systems, defect inspection tools, and yield management platforms.

This data explosion has created an opportunity for artificial intelligence and machine learning to become foundational technologies within semiconductor manufacturing. Modern fabs operate thousands of process steps with highly interdependent variables, making traditional rule-based optimization insufficient. Machine learning models can analyze terabytes of sensor data in real time to identify hidden process correlations, predict equipment failures, and optimize wafer yields. Predictive maintenance algorithms, for example, use telemetry data from deposition, etching, and lithography equipment to forecast tool degradation before catastrophic failures occur. This minimizes downtime and improves overall equipment effectiveness (OEE).

Another critical area discussed is design-technology co-optimization (DTCO). Historically, chip design and manufacturing were treated as relatively independent domains. However, advanced nodes now require deep integration between EDA workflows, process technologies, and packaging architectures. AI-assisted EDA tools are increasingly used to accelerate place-and-route optimization, power integrity analysis, and timing closure. Generative AI models are also being explored for automated verification, layout synthesis, and defect prediction. These approaches significantly reduce engineering iteration cycles while improving design quality and manufacturability.

The panel also emphasized the growing importance of advanced packaging technologies as a continuation of Moore’s Law. Chiplet-based architectures, 2.5D integration, and 3D stacking allow manufacturers to improve system performance without relying entirely on transistor shrink. High-bandwidth interconnects, through-silicon vias (TSVs), and heterogeneous integration enable CPUs, GPUs, memory, and accelerators to be combined into tightly integrated systems. This architecture is especially important for AI workloads, where memory bandwidth and interconnect efficiency are often more critical than raw transistor density.

Data infrastructure was identified as another strategic requirement for future semiconductor manufacturing. AI-driven fabs depend on scalable, low-latency storage systems capable of supporting high-throughput analytics pipelines. Semiconductor workflows involve distributed simulation environments, petabyte-scale datasets, and collaborative global engineering teams. Cloud-integrated storage architectures and high-performance parallel file systems are increasingly necessary to support EDA simulations, digital twins, and manufacturing analytics. Digital twins, in particular, allow fabs to model process behavior virtually, enabling rapid experimentation and optimization before physical implementation.

Cybersecurity and supply chain resilience were also addressed as emerging priorities. Semiconductor manufacturing is highly globalized, with dependencies across materials suppliers, foundries, packaging vendors, and equipment manufacturers. AI-enabled visibility into supply chain operations can help predict disruptions, optimize inventory, and improve production planning. At the same time, protecting intellectual property and manufacturing data has become critical as fabs adopt cloud-connected infrastructures.

Bottom line: The future of semiconductor manufacturing intelligence lies in the convergence of AI, data engineering, advanced process technologies, and heterogeneous system integration. The industry is transitioning from pure transistor scaling toward intelligent optimization across the entire semiconductor lifecycle. Success in this next era will depend not only on physics and materials science but also on the ability to extract actionable insights from massive manufacturing datasets. Semiconductor leaders that effectively combine AI-driven analytics with scalable infrastructure and advanced packaging technologies will define the next generation of computing innovation.

See the Replay Here.

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