I’m a fan of DVCon, a fan of Accellera and a fan of Munich, hosting DVCon Europe once again. This year’s event runs from November 14th through 15th (with some events on the 16th) at the Holiday Inn Munich in the City Center. Phillippe Notton (CEO, SiPearl) will deliver a keynote on “Energy Efficient High-Performance Computing in the Heart of Europe”, and Michaela Blott (Sr. Fellow at AMD Research) will deliver a second keynote on “Pervasive and Sustainable AI with Adaptive Computing”. Add to that a medley of Accellera updates and EDA, semiconductor, and EDA+semiconductor talks on a variety of topics. I’ll briefly summarize Accellera-related topics below, remembering that, as is normal with standards, detail is hard to come by until officially released. Remember to REGISTER.
Functional safety working group update
This working group is chaired by Alessandra Nardi, a well-respected authority in the safety domain. The group aims to standardize methods to capture and propagate safety intent from system (a car for example) down through software, SoC and IP design, ensuring ability to exchange data and to support traceability between multiple levels of total system design. This working group will release a white paper soon which they will discuss in the session.
Workshops on UVM-AMS and CDC/RDC
These are areas I am watching closely. In AMS, Accellera is working on both mixed signal modeling and UVM-AMS; in this event they will elaborate on the latter. This technical workshop will walk the audience through a worked example to illustrate key pieces of this approach and give a preview of how this standard will expand the ecosystem for AMS verification to allow vendors and users to create and share compatible verification components and use them in existing UVM environments. Well worth attending, I think.
The CDC/RDC (reset domain crossing) session starts with an intro to the basics on domain crossings. The second half will be another must-see for anyone working with IP verified against one CDC/RDC tool which must be verified at the system level using a different CDC/RDC tool. A demo will highlight different steps of the CDC verification flow. A small and illustrative RTL test case with at least two EDA verification tools will be used to raise awareness about the importance of a new standard to make CDC models portable and reusable between different tools.
IP-XACT and SystemC
IP-XACT has been around for a while and is well-accepted as a standardized format for IP meta data relevant to integration, but how widely is it used as an integration platform? The IP-XACT discussion comes in two parts, starting with a tutorial on the basics of the standard including aspects relevant to integration and the hardware/software interface. The second part addresses industrial practices from EDA vendors, IP providers, and IP integrators: Agnisys, Arteris, Infineon, and Intel. That I think should be very interesting – I’m always eager to hear more about IP-XACT integration practices in production.
There is also a SystemC evolution day planned to review upcoming standard advances and for experts in the field to network and exchange ideas.
AI panel (because AI)
You can’t have a conference these days without an AI topic. Accellera chair Lu Dai features as a panelist on this panel, titled “All AI All the Time”. They will discuss how AI can best be applied in verification objectives. I’m sure discussion will be fairly free ranging 😊Share this post via: