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August 1, 2018

AMS Experts Share IC Design Stories at #55DAC

AMS Experts Share IC Design Stories at #55DAC
by Daniel Payne on 08-01-2018 at 7:00 am
Categories: EDA, Synopsys

At #55DAC in SFO the first day is always the busiest on the exhibit floor, so Monday by lunch time I was hungry and took a short walk to the Marriott hotel nearby to listen to AMS experts from several companies talk about their EDA tool use, hosted by Synopsys:

Samsung
Toshiba Memory Corp.
NVIDIA
Seagate
Numem
Esperanto

May 29, 2018

Innovation in a Commodity Market

Innovation in a Commodity Market
by Bernard Murphy on 05-29-2018 at 7:00 am
Categories: Cadence, EDA

Logic simulation is a victim of its own success. It has been around for at least 40 years, has evolved through multiple language standards and has seen significant advances in performance and major innovations in testbench standards. All that standardization and performance improvement has been great for customers but can present… Read More

December 12, 2017

Creative Noise-Reduction in Automotive AMS

Creative Noise-Reduction in Automotive AMS
by Bernard Murphy on 12-12-2017 at 7:00 am
Categories: ANSYS, Inc., Automotive, EDA

Automotive applications are one of the hottest domains today in semiconductor design. We’re bombarded daily with articles on new hybrids, electric cars, ADAS and autonomous cars, trucks and busses. All of these applications are certainly amazing, but the devices that make them work still have to deal with the same old challenges,… Read More

November 6, 2017

Webinars: Bumper Pack of AMS Webinars from ANSYS

Webinars: Bumper Pack of AMS Webinars from ANSYS
by Bernard Murphy on 11-06-2017 at 12:00 pm
Categories: ANSYS, Inc., EDA, Events

Power integrity and reliability are just as important for AMS designs as they are for digital designs. Ansys is offering a series of five webinars on this topic, under a heading they call ANSYS in ACTION, a bi-weekly demo series from ANSYS in which an application engineer shows you how simulation can address common applications.… Read More

October 24, 2017

Silicon Creations talks about 7nm IP Verification for AMS Circuits

Silicon Creations talks about 7nm IP Verification for AMS Circuits
by Daniel Payne on 10-24-2017 at 12:00 pm
Categories: EDA, FinFET, Mentor, a Siemens Business

Designing at 7nm is a big deal because of the costs to make masks and then produce silicon that yields at an acceptable level, and Silicon Creations is one company that has the experience in designing AMS IP like: PLL, Serializer-Deserializer, IOs, Oscillators. Why design at 7nm? Lots of reasons – lower power, higher speeds,… Read More

October 2, 2017June 14, 2019

TSMC Teamwork Translates to Technical Triumph

TSMC Teamwork Translates to Technical Triumph
by Tom Simon on 10-02-2017 at 12:00 pm
Categories: Foundries, IP, Mentor, a Siemens Business, Silicon Creations, TSMC

Most people think that designing successful high speed analog circuits requires a mixture of magic, skill and lots of hard work. While this might be true, in reality it also requires a large dose of collaboration among each of the members of the design, tool and fabrication panoply. This point was recently made abundantly clear … Read More

April 1, 2017

Everything a Designer Wants to Ask About FDSOI

Everything a Designer Wants to Ask About FDSOI
by Adele Hars on 04-01-2017 at 12:00 pm
Categories: EDA, Events, FD-SOI

So you’ve got questions about FD-SOI? For chip designers in Silicon Valley, there’s a great opportunity to get answers from some of the world’s leading design experts. It’s coming up fast: April 14th, the SOI Consortium is organizing a full day of FDSOI tutorials for chip designers. Bear in mind that … Read More

March 31, 2017June 14, 2019

Lowering Costs for Custom SoC Development – ARM and Tanner EDA

Lowering Costs for Custom SoC Development – ARM and Tanner EDA
by Daniel Payne on 03-31-2017 at 12:00 pm
Categories: ARM, EDA, IoT, IP, Mentor, a Siemens Business, Tanner EDA

Cost is a major barrier when an electronic design company starts to consider developing a custom SoC for a particular market segment. But what if there was a way to lower the development cost, or even get to an SoC proof of concept for no cost except of course for your engineering expenses? That value proposition caught my attention… Read More

January 11, 2017June 14, 2019

Tool Trends Highlight an Industry Trend for AMS designs

Tool Trends Highlight an Industry Trend for AMS designs
by Bernard Murphy on 01-11-2017 at 7:00 am
Categories: Automotive, ClioSoft, EDA

Archaeologists often use tools found in digs as a major indicator of trends in civilizations. The same could be said for trends in design, though we don’t have to reconstruct these design trends – we tend to see them ahead of us.
The trend in this case is the growing importance of sensors in designs and there’s no better example of that… Read More

November 21, 2016June 14, 2019

Mentor DefectSim Seen as Breakthrough for AMS Test

Mentor DefectSim Seen as Breakthrough for AMS Test
by Mitch Heins on 11-21-2016 at 4:00 pm
Categories: Automotive, EDA, Mentor, a Siemens Business

For decades, digital test has been fully automated including methodologies and automation for test pattern generation, grading and test time compression. Automation for analog and mixed-signal (AMS) IC test has not however kept pace. This is troubling as according to IBSapproximately 85% of SoC design starts are now AMS designs.… Read More

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Tag: ams

AMS Experts Share IC Design Stories at #55DAC

Innovation in a Commodity Market

Creative Noise-Reduction in Automotive AMS

Webinars: Bumper Pack of AMS Webinars from ANSYS

Silicon Creations talks about 7nm IP Verification for AMS Circuits

TSMC Teamwork Translates to Technical Triumph

Everything a Designer Wants to Ask About FDSOI

Lowering Costs for Custom SoC Development – ARM and Tanner EDA

Tool Trends Highlight an Industry Trend for AMS designs

Mentor DefectSim Seen as Breakthrough for AMS Test

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VLSI Design Methodology Development Webinar Replay and Follow up Q&A!

Memory Forecast to Account for 43% of Total 2019 Semi Spending

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Materials Engineer, PhD with 6+ years experience aiming for Process Development or R&D