Cadence Debuts Dynamic Duo III with a Basket of Goodies

Cadence Debuts Dynamic Duo III with a Basket of Goodies
by Bernard Murphy on 04-18-2024 at 6:00 am

Dynamic Duo III min

I am a fan of product releases which bundle together multiple high-value advances. That approach reduces the frequency of releases (no bad thing) in exchange for more to offer per release, better proven through solid partner validation. The Dynamic Duo III release falls in this class, offering improvements in performance, capacity,… Read More


Checking and Fixing Antenna Effects in IC Layouts

Checking and Fixing Antenna Effects in IC Layouts
by Daniel Payne on 03-14-2024 at 10:00 am

Planar CMOS cross-section – antenna DRC

IC layouts go through extensive design rule checking to ensure correctness, before being accepted for fabrication at a foundry or IDM. There’s something called the antenna effect that happens during chip manufacturing where plasma-induced damage (PID) can lower the reliability of MOSFET devices. Layout designers run Design… Read More


Mastering Mixed-Signal Verification with Siemens Symphony Platform

Mastering Mixed-Signal Verification with Siemens Symphony Platform
by Daniel Payne on 01-17-2024 at 10:00 am

verification platform min

Digital design and verification is well understood by EDA vendors and IC designers, however mixed-signal design and verification is more challenging, because the continuous nature of analog signals requires more compute resources and specialized design skills. Siemens EDA has a unique offering in what they call SymphonyRead More


DVCon Europe is Coming Soon. Sign Up Now

DVCon Europe is Coming Soon. Sign Up Now
by Bernard Murphy on 10-31-2023 at 6:00 am

logo accellera min

I’m a fan of DVCon, a fan of Accellera and a fan of Munich, hosting DVCon Europe once again. This year’s event runs from November 14th through 15th (with some events on the 16th) at the Holiday Inn Munich in the City Center. Phillippe Notton (CEO, SiPearl) will deliver a keynote on “Energy Efficient High-Performance Computing in the… Read More


SRAM design analysis and optimization

SRAM design analysis and optimization
by Daniel Payne on 10-24-2023 at 6:00 am

SRAM design cell min

Every year EDA vendor MunEDA hosts a user group meeting where engineers present how they used automation tools to improve their IC designs, and one presentation from Peter Huber of Infineon caught my attention, it was all about SRAM design optimization. Peter has authored papers at IEEE conferences and been issued patents related… Read More


Accellera Update: CDC, Safety and AMS

Accellera Update: CDC, Safety and AMS
by Bernard Murphy on 07-06-2022 at 6:00 am

logo accellera min

I recently had an update from Lu Dai, Chairman of Accellera, also Sr. Director of Engineering at Qualcomm. He’s always a pleasure to talk to, in this instance giving me a capsule summary of status in 3 areas that interested me: CDC, Functional Safety and AMS. I will start with CDC, a new proposed working group in Accellera. To manage… Read More


Lecture Series: Designing a Time Interleaved ADC for 5G Automotive Applications

Lecture Series: Designing a Time Interleaved ADC for 5G Automotive Applications
by Kalar Rajendiran on 11-01-2021 at 6:00 am

Slide AMS Lecture Series Snapshot

A recent educational virtual event with the above title was jointly sponsored by Synopsys and Global Foundries. The objective was to bring awareness to state-of-the-art mixed-signal design practices for automotive circuits. The 2-day event comprised of lectures delivered by engineering professors and doctoral students… Read More


Trust, but verify. How to catch peanut butter engineering before it spreads into your system — Part 2: Verification.

Trust, but verify. How to catch peanut butter engineering before it spreads into your system — Part 2: Verification.
by Raul Perez on 02-09-2021 at 10:00 am

iStock 1176843522

This article about verification is part 2 of a two article series. Please see part 1 on validation HERE.

Verification is a field that has emerged as its own discipline. It’s no longer being relegated to an activity led by the design team to which time is allocated as long as it doesn’t get in the way of designing. Chip companiesRead More


The Tech Week that was January 13-17 2020

The Tech Week that was January 13-17 2020
by Mark Dyson on 01-19-2020 at 10:00 am

Semiconductor Weekly Summary 1

In a week where the “phase 1” trade deal between US and China was finally signed, here is all the key news from the semiconductor and technology sector around the world.

After 2 years of an ever increasing trade war, the US and China have signed the so called Phase 1 deal aimed at reducing trade frictions.

Just as important as what is … Read More


Calibre Commences Cloud Computing

Calibre Commences Cloud Computing
by Tom Simon on 11-06-2019 at 10:00 am

Calibre was a big game changer for DRC users when it first came out. Its hierarchical approach dramatically shortened runtimes with the same accuracy as other existing, but slower, flat tools. However, one unsung part of this story was that getting Calibre up and running required minimal effort for users. Two things are required… Read More