Calibre Commences Cloud Computing

Calibre Commences Cloud Computing
by Tom Simon on 11-06-2019 at 10:00 am

Calibre was a big game changer for DRC users when it first came out. Its hierarchical approach dramatically shortened runtimes with the same accuracy as other existing, but slower, flat tools. However, one unsung part of this story was that getting Calibre up and running required minimal effort for users. Two things are required… Read More


Automating Timing Arc Prediction for AMS IP using ML

Automating Timing Arc Prediction for AMS IP using ML
by Daniel Payne on 10-16-2019 at 6:00 am

NVIDIA designs some of the most complex chips for GPU and AI applications these days, with SoCs exceeding 21 billion transistors. They certainly know how to push the limits of all EDA tools, and they have a strong motivation to automate more manual tasks in order to quicken their time to market. I missed their Designer/IP Track Poster… Read More


AMS Experts Share IC Design Stories at #55DAC

AMS Experts Share IC Design Stories at #55DAC
by Daniel Payne on 08-01-2018 at 7:00 am

At #55DAC in SFO the first day is always the busiest on the exhibit floor, so Monday by lunch time I was hungry and took a short walk to the Marriott hotel nearby to listen to AMS experts from several companies talk about their EDA tool use, hosted by Synopsys:

  • Samsung
  • Toshiba Memory Corp.
  • NVIDIA
  • Seagate
  • Numem
  • Esperanto

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Innovation in a Commodity Market

Innovation in a Commodity Market
by Bernard Murphy on 05-29-2018 at 7:00 am

Logic simulation is a victim of its own success. It has been around for at least 40 years, has evolved through multiple language standards and has seen significant advances in performance and major innovations in testbench standards. All that standardization and performance improvement has been great for customers but can present… Read More


Creative Noise-Reduction in Automotive AMS

Creative Noise-Reduction in Automotive AMS
by Bernard Murphy on 12-12-2017 at 7:00 am

Automotive applications are one of the hottest domains today in semiconductor design. We’re bombarded daily with articles on new hybrids, electric cars, ADAS and autonomous cars, trucks and busses. All of these applications are certainly amazing, but the devices that make them work still have to deal with the same old challenges,… Read More


Webinars: Bumper Pack of AMS Webinars from ANSYS

Webinars: Bumper Pack of AMS Webinars from ANSYS
by Bernard Murphy on 11-06-2017 at 12:00 pm

Power integrity and reliability are just as important for AMS designs as they are for digital designs. Ansys is offering a series of five webinars on this topic, under a heading they call ANSYS in ACTION, a bi-weekly demo series from ANSYS in which an application engineer shows you how simulation can address common applications.… Read More


Silicon Creations talks about 7nm IP Verification for AMS Circuits

Silicon Creations talks about 7nm IP Verification for AMS Circuits
by Daniel Payne on 10-24-2017 at 12:00 pm

Designing at 7nm is a big deal because of the costs to make masks and then produce silicon that yields at an acceptable level, and Silicon Creations is one company that has the experience in designing AMS IP like: PLL, Serializer-Deserializer, IOs, Oscillators. Why design at 7nm? Lots of reasons – lower power, higher speeds,… Read More


TSMC Teamwork Translates to Technical Triumph

TSMC Teamwork Translates to Technical Triumph
by Tom Simon on 10-02-2017 at 12:00 pm

Most people think that designing successful high speed analog circuits requires a mixture of magic, skill and lots of hard work. While this might be true, in reality it also requires a large dose of collaboration among each of the members of the design, tool and fabrication panoply. This point was recently made abundantly clear … Read More


Everything a Designer Wants to Ask About FDSOI

Everything a Designer Wants to Ask About FDSOI
by Adele Hars on 04-01-2017 at 12:00 pm

So you’ve got questions about FD-SOI? For chip designers in Silicon Valley, there’s a great opportunity to get answers from some of the world’s leading design experts. It’s coming up fast: April 14th, the SOI Consortium is organizing a full day of FDSOI tutorials for chip designers. Bear in mind that Read More


Lowering Costs for Custom SoC Development – ARM and Tanner EDA

Lowering Costs for Custom SoC Development – ARM and Tanner EDA
by Daniel Payne on 03-31-2017 at 12:00 pm

Cost is a major barrier when an electronic design company starts to consider developing a custom SoC for a particular market segment. But what if there was a way to lower the development cost, or even get to an SoC proof of concept for no cost except of course for your engineering expenses? That value proposition caught my attention… Read More