PVT and Statistical Design in Nanometer Process Geometries

PVT and Statistical Design in Nanometer Process Geometries
by Daniel Nenni on 09-18-2011 at 9:00 am

On Sept 22, 2011, the nm Circuit Verification Forumwill be held in Silicon Valley, hosted by Berkeley Design Automation. At this forum, Trent McConaghy of Solido DA will present a case study on the TSMC Reference Flow 2.0 VCO circuit, to showcase Fast PVT in the steps of extracting PVT corners, verifying PVT, and doing post-layout… Read More


Nanometer Circuit Verification Forum

Nanometer Circuit Verification Forum
by Daniel Nenni on 08-29-2011 at 2:33 pm

Verifying circuits on advanced process nodes has always been difficult, and it’s no easier with today’s nanometer CMOS processes. There’s a great paradox in nanometer circuit design and verification. Designers achieve their greatest differentiation when they implement analog, mixed-signal, RF and custom … Read More


Totem webinar: Analog/Mixed-Signal Power Noise and Reliability

Totem webinar: Analog/Mixed-Signal Power Noise and Reliability
by Paul McLellan on 07-30-2011 at 5:26 pm

The Totem webinar will be at 11am on Tuesday 2nd August. This session will be conducted by Karan Sahni, Senior Applications Engineer at Apache Design Solutions. Karan has been with Apache since 2008, supporting the Redhawk, Totem, Sentinel product lines. He received his MS in Electrical Engineering from the Syracuse University… Read More


Want to learn Mixed-Signal Design and Verification?

Want to learn Mixed-Signal Design and Verification?
by Daniel Payne on 07-20-2011 at 6:13 pm

Workshops are a great where to learn hands-on about IC design technology. Mentor has a free workshop to introduce you to creating, simulating and verifying mixed-signal (Analog and Digital) designs.

PLL waveforms showing both digital and analog signals.

Dates in Fremont, California
July 26, 2011
September 15, 2011
November… Read More


Circuit Simulation and IC Layout update from Mentor at DAC

Circuit Simulation and IC Layout update from Mentor at DAC
by Daniel Payne on 06-17-2011 at 7:06 pm

Intro
On Monday evening I talked with Linda Fosler, Director of marketing for the DSM Division at Mentor about what’s new at DAC this year in circuit simulation and IC layout tools.

Notes
IC Station – old name for IC layout tools

Eldo – Eldo Classic- Cell characterization
– ST is the early customer and teaching customer,… Read More


Custom and AMS Design

Custom and AMS Design
by Daniel Payne on 02-21-2011 at 10:06 pm

Samsung%203DIC%20Roadmap

For IC designers creating full-custom or AMS designs there are plenty of challenges to getting designs done right on the first spin of silicon. Let me give you a sneak peek into what’s being discussed at the EDA Tech Forum in Santa Clara, CA on March 10th that will be of special interest to you:

3D TSV (Through Silicon Vias) are… Read More