Recently I was researching the keynote speeches of isQED (International Society for Quality Electronic Design) Symposium 2012 and saw the very first, great presentation, “Taming the Challenges in Advanced Node Design” by Tom Beckley, Sr. VP at Cadence. I know Tom very well as I have worked with him and I admire his knowledge, authority and leadership in analog and mixed-signal domain. Inspired by his presentation, I became curious and further read his detailed speech put into blogs at EDA360 page. It was great pleasure going through the astounding collection of details and ideas there. I read it twice very minutely.
As Custom IC, AMS, Physical Design has been my core expertise; it reminded me about one of my article, “Need and Opportunity for Higher Analog Automation” in early Feb. In that article my emphasis was on systematic variation and layout dependent effects at lower nodes, which are primarily analog specific depending on device parameters and their relative placement, thereby making it essential to automate the detection and correction of such effects early in the design cycle. It is heartening to see Cadence coming up with Rapid Prototyping methodology to develop design building blocks called ‘modgens’ which account for layout dependent effects, parasitics and new P&R rules at 20nm, the methodology even uses double patterning technology to increase the routing pitch.
It’s great methodology which can address mega function generation employing automatic detection of analog structures like current mirror and differential pair from schematic and generating layout followed by extraction and verification. Using these building blocks for higher level design can serve the purpose, but not in all cases. Preserving the placement constraints to re-construct the layout with any changes is fine till ECO, but that cannot be employed for large changes. If we look at the problem from design perspective, in today’s context, at 20nm, a typical analog IP block could be big in the range of 40000 to 50000 transistors. Clearly and specifically knowing that analog design can be an ocean of secrets, all of that may not rightly fit into the scheme of rapid prototyping building blocks into abstracts and then assembling them. Even if 75% to 80% of that fits into the building block level automation, the rest 20% (about 10000 transistors) needs to be done by hand which would be a substantial task considering the effects and complexities with each transistor at 20nm we talked about. At 14nm, it is going to be tougher. This leaves us at the same place we were with manual looping between circuit and layout.
Considering the design perspective, it needs a general approach to placement and routing the analog design with due attention to 20nm issues. In my article, I had also talked about the need for a general approach to analog automation based on an open standard analog constraint format which includes design constraints for symmetry, matching, shielding, placement, floorplanning, routing, clocking, timing, and electrical and so on. Of course, the abstraction approach solves the problem to great extent, but for completeness of the design, it needs a general automation applicable to the whole design. Once that becomes available, that can take the centre place.
Comments from design and EDA community are welcome. I would be happy to know if there are more new ideas for analog automation.Share this post via: