Toshio Nakama is the founder and the CEO of S2C and also a strong advocate of FPGA accelerated ASIC/SoC design methodology. Mr. Nakama devotes much of his time in promoting scalable Prototyping/Emulation hardware architecture and defining automated software specifications. He first started his career at Altera in 1997 and served in technical and sales management roles at Aptix Corporation from 1998 to 2003. He co-founded S2C in Silicon Valley in 2003 and established R&D and manufacturing teams in Shanghai, China in 2004. S2C was acquired by SMiT Group in 2018 and continues to be a leading global provider of FPGA prototyping solutions. Mr. Nakama holds a bachelor’s degree in Electrical Engineering from Cornell University and an EMBA degree from CEIBS.
What brought you to the semiconductor industry?
I was first introduced to FPGAs in my Digital Circuit Design course at Cornell and I was immediately drawn to the programmability and the vast application aspects of FPGAs. This led me to join Altera and later Aptix, who was known for FPIC (Field Programmable Interconnect Chips). FPICs were often used in conjunction with FPGAs as solutions for reconfigurable computing and IC design emulation. The immense value such as convenience, productivity and flexibility demonstrated by these programmable devices eventually became my mission – to push the limits of what FPGA prototyping can do and to make the IC verification process easier, faster, and more efficient for IC designers.
Can you tell us about the origin of S2C?
Two other ex-Aptix principals and I, together with another finance professional – we pooled our money and founded S2C in 2003. At the time, most of the focus on IC design verification was with software simulation and hardware emulation. FPGA-based prototyping on the other hand was yet to be a mainstream verification methodology and it was only accessible by large design houses with the budget and resources to materialize a prototyping architecture. We recognized the value of prototyping and the power to accelerate time-to-success for SoC design companies.
Also at the time, we saw a new wave of Asian firms, as well as Asian design centers for US/European companies taking shape. We expected that these new companies were to be more open to new ideas and new EDA tools from a new innovator. In 2004, we set up a R&D center in Shanghai to gain better access to talent pools for upcoming product developments and to better connect and service the Asian customers. The latter is particularly important as the methodology behind FPGA-based prototyping was fairly new and there would be a fair amount of customer handholding required.
From the start, S2C was not just another “FPGA board” vendor but we aimed to bring convenience, productivity, and flexibility to shorten the verification cycle. One key challenge at hand when we started was the development of tools and IPs specifically for FPGA-based prototyping. In particular, FPGA tools were different, even foreign to most ASIC designers. S2C’s first task was to develop a complete methodology – a set of tools and IP that would not only make FPGA-based prototyping more productive but would also smooth out the transition of a design from the prototyping stage back into an EDA flow bound for an SoC.
In February 2005, S2C filed its patent for a “Scalable reconfigurable prototyping system and method.” It described a system for automating validation tasks for SoCs, with a user workstation, data communication interface, and an emulation platform with multiple FPGAs plus interfaces to a real-world target system. In May 2005, S2C announced its first product the IP Porter system at DAC. Beta customers working with the product estimated their design time was cut by 3 to 6 months.
What markets and what are some of the customer challenges does S2C address today?
As mentioned, our key mission has always been to help customers shorten their time-to-success through hardware-accelerated verification solutions. We now see that many of the high complexity ASIC designs today come from markets such as AI, Datacenter, Multimedia, Networking and Automotive These are often hyperscale multi-core SOC designs with time consuming software development and testing requirements. FPGA-based prototyping is the optimal solution to provide a high performance platform not only for hardware validation but also as an early prototype to enable software teams to conduct hardware/software co-development and co-testing.
To target hyperscale designs, we launched Prodigy Logic Matrix in late 2020. Logic Matrix is a high-density FPGA prototyping platform designed for multi-system expansion to address the needs for both capacity and performance. Earlier this quarter, we also announced MDM Pro, the latest member of our Multi-FPGA debugging solution. MDM Pro increases the concurrent deep trace capability to 8 FPGAs and supports faster sampling rates and deeper trace capacity. We are also continuously refining our partitioning software to and releasing more off-the-shelf daughter cards to simplify the setup of customer’s prototyping environment and to enable testing done via real-world data.
What is the S2C competitive positioning?
There is a combination of things which is raising S2C to new heights. With close to 20 years of know-how and proven track record, solid products, close customer relationship and outstanding service, we are doing extremely well in China, where the IC design activities have grown rapidly over the last few years. These customers not only help to provide scale of economy to lower cost, they also in turn help to provide feedback to enable us to continuously innovate and to roll our new products to match the market demand – not only for China customers but for customers worldwide, at good value.
If we compare ourselves to the Big 3, while S2C may not have the same comprehensive EDA coverage as they do, we are however more agile and more flexible. We aim to service and provide customization to help address customer demands. If we compare S2C to other tier two vendors and BYO (Build Your Own), S2C’s products are proven, more robust, more comprehensive. Together with scale of economy, we deliver high values to our customers.
What does the next twelve months have in store for S2C EDA?
2021 will be an exciting year for S2C. On the hardware side, we are rolling out a higher capacity Logic Matrix LX2 in Q3 and our first emulator platform in Q4. On the software side we will be adding RTL partitioning and serdes based pinmux support in a few months to better service hyperscale designs.
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