S2C Targets Faster RISC-V Bring-Up With Prototyping and AI

S2C Targets Faster RISC-V Bring-Up With Prototyping and AI
by Daniel Nenni on 10-27-2026 at 6:00 am

S2C advances RISC V FPGA development

S2C showcased FPGA prototyping and AI-assisted debugging at the sixth RISC-V Summit China, outlining how developers can validate complex processor designs and begin software development before first silicon. Its demonstrations connected three stages of that effort: running substantial RISC-V systems on FPGA hardware,… Read More


CTO Interview with Sirish Munipalli of Moores Lab AI

CTO Interview with Sirish Munipalli of Moores Lab AI
by Daniel Nenni on 10-14-2026 at 12:00 pm

Agentic AI for chip verification

Sirish Munipalli is Co-Founder and CTO of Moores Lab AI, where he leads the development of agentic AI for chip design verification, including SpecAgent(tm), the company’s specification and modeling platform. He has spent about 15 years designing and verifying complex silicon: FPGA prototyping at Intel, post-silicon validation… Read More


S2C Prodigy Complete Prototyping Solutions—and Why They Matter

S2C Prodigy Complete Prototyping Solutions—and Why They Matter
by Daniel Nenni on 09-24-2026 at 10:00 am

S2C Prodigy Complete Prototyping Solutions—and Why They Matter

Modern system-on-chip (SoC) and application-specific integrated circuit (ASIC) designs are extraordinarily complex. They may combine processors, accelerators, memory controllers, high-speed interfaces, security functions, and millions—or even billions—of logic gates. Verifying these systems entirely through … Read More


Unified Emulation and Prototyping: Pipedream or Reality?

Unified Emulation and Prototyping: Pipedream or Reality?
by Lauro Rizzatti on 09-03-2026 at 10:00 am

Unified Emulation and Prototyping Pipedream or Reality Figure 1

Preamble
Hardware-assisted verification (HAV) platforms, including hardware emulators and FPGA-based prototyping systems, are the two dominant methodologies for validating long workloads on complex System-on-Chip (SoC) designs before tape-out. HAV sits within a broader continuum of verification engines: simulation… Read More


Shift Left with S2C Prodigy: From RTL Verification to Real-World Software Validation

Shift Left with S2C Prodigy: From RTL Verification to Real-World Software Validation
by Daniel Nenni on 08-04-2026 at 10:00 am

HAV

For modern SoC teams, “shift left” no longer means finding a few more RTL bugs before tape-out. It means moving meaningful system validation earlier—far enough left that firmware, operating systems, drivers, applications, and external interfaces can be exercised before first silicon arrives. This change is essential as software… Read More


When Software Outruns Silicon: Hardware-Assisted Test Generation to the Rescue

When Software Outruns Silicon: Hardware-Assisted Test Generation to the Rescue
by Lauro Rizzatti on 06-29-2026 at 2:00 pm

When Software Outruns Silicon Figure 1

For the past decade, the semiconductor industry has been moving in one direction: shift-left, specifically, shifting more validation into the pre-silicon phase. The idea was straightforward: if software ultimately determines how a system behaves, then software should become a primary vehicle for verification.

The industry… Read More


Technical Paper: FPGA Prototyping That Creates Useful PreSilicon Evidence

Technical Paper: FPGA Prototyping That Creates Useful PreSilicon Evidence
by Daniel Nenni on 06-11-2026 at 6:00 am

FPGA Prototyping Beyond RTL Fit Building Useful Pre Silicon Evidence

As semiconductor designs continue to grow in complexity, FPGA prototyping has become an essential component of modern pre-silicon validation strategies. While FPGA capacity and gate-count equivalence often dominate discussions around prototyping platforms, the true value of an FPGA prototype lies elsewhere: its ability… Read More


From Wooden Boards to White Gloves: How FPGA Prototyping and Emulation Became Two Worlds of Verification… and How the Convergence Is Unfolding

From Wooden Boards to White Gloves: How FPGA Prototyping and Emulation Became Two Worlds of Verification… and How the Convergence Is Unfolding
by Lauro Rizzatti on 04-13-2026 at 6:00 am

From Wooden Boards to White Gloves Table 1 (1)

FPGA prototyping and hardware emulation originated from two independent demands that emerged at roughly the same time, namely, the necessity to implement digital designs in reconfigurable hardware. This was conceivable given the newly introduced field programmable gate array (FPGA) device.

Yet from the very beginning they… Read More


Hardware is the Center of the Universe (Again)

Hardware is the Center of the Universe (Again)
by Lauro Rizzatti on 02-23-2026 at 10:00 am

Hardware is the Center of the Universe (Again) Figure 1

The 40-Year Evolution of Hardware-Assisted Verification — From In-Circuit Emulation to AI-Era Full-Stack Validation

For more than a decade, Hardware-Assisted Verification platforms have been the centerpiece of the verification toolbox. Today, no serious semiconductor program reaches tapeout without emulation or FPGA-prototyping… Read More


Accellera Strengthens Industry Collaboration and Standards Leadership at DVCon U.S. 2026

Accellera Strengthens Industry Collaboration and Standards Leadership at DVCon U.S. 2026
by Daniel Nenni on 02-10-2026 at 10:00 am

DVCON 2026

At DVCon U.S. 2026, Accellera Systems Initiative reinforces its central role in shaping the future of electronic design and verification through a focused program of workshops, tutorials, and community engagement. As system complexity continues to rise across AI, automotive, HPC, and communications markets, the need for… Read More