The Quiet Giant in Verification IP and More

The Quiet Giant in Verification IP and More
by Mike Gianfagna on 04-21-2020 at 10:00 am

SmartDV Market Coverage

In the technology industry, we’re all used to the hype about the latest and greatest. Semiconductor IP participates in the over-drive news cycle from time to time as well. So, when I see a company that has real, solid credentials but has resisted the temptation to over-hype, it gets my attention. I had an experience like this recently… Read More


Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards

Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards
by Daniel Nenni on 03-09-2020 at 6:00 am

Aldec Webinar SemiWiki

Before starting your next FPGA Prototyping Project you should catch the next SemiWiki webinar – “Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards”, in partnership with Aldec.

A significant portion of my  30+ years in the EDA industry has revolved around design verification with some form of FPGA … Read More


S2C Delivers FPGA Prototyping Solutions with the Industry’s Highest Capacity FPGA from Intel!

S2C Delivers FPGA Prototyping Solutions with the Industry’s Highest Capacity FPGA from Intel!
by Daniel Nenni on 11-19-2019 at 6:00 am

In 2016 we published our book “Prototypical: The Emergence of FPGA-Based Prototyping for SoC Design” which began an incredible journey through ASIC prototyping. While we are working on an update to that book there is some recent Prototyping news that is worthy of praise.

First and foremost, S2C Inc. has just announced THE single… Read More


WEBINAR: How ASIC/SoC Rapid Prototyping Solutions Can Help You!

WEBINAR: How ASIC/SoC Rapid Prototyping Solutions Can Help You!
by Daniel Nenni on 09-17-2019 at 10:00 am

Today’s off-the-shelf FPGA based prototyping systems have established their value in every stage of the application specific integrated circuit (ASIC) and system-on-chip (SoC) design flow. Moving beyond traditional applications such as in-circuit testing and early software development, this technology has expanded … Read More


AI Chip Prototyping Plan

AI Chip Prototyping Plan
by Daniel Nenni on 09-10-2019 at 6:00 am

I recently had the opportunity to sit down with a chip designer for an AI start-up to talk about using FPGA prototyping as part of a complex silicon verification strategy. Like countless other chip designers for whom simulation alone simply does not provide sufficient verification coverage, this AI start-up also believed that… Read More


WEBNAR: How ASIC/SoC Rapid Prototyping Solutions Can Help You!

WEBNAR: How ASIC/SoC Rapid Prototyping Solutions Can Help You!
by Daniel Nenni on 08-23-2019 at 10:00 am

If you are considering an FPGA prototype for an ASIC or SoC as part of your verification strategy, which more and more chip designers today are doing to enhance verification coverage of complex designs, please take advantage of this webinar replay:

How ASIC/SoC Prototyping Solutions Can Help You!

Or to get a quick quote from S2C Read More


Are the 100 Most Promising AI Start-ups Prototyping?

Are the 100 Most Promising AI Start-ups Prototyping?
by Daniel Nenni on 07-12-2019 at 10:00 am

I came across a report on the 100 most promising AI start-ups. The report claimed that CBInsights had “selected the 100 most promising AI start-ups from a pool of 3K+ companies based on several factors …”  Wait, what … 3K+ companies!?!?  This was a stunning reminder of the sheer magnitude of what is shaping up to be a veritable tsunami… Read More


FPGA Prototyping for AI Product Development

FPGA Prototyping for AI Product Development
by Randy Smith on 06-21-2019 at 8:00 am

I recently wrote about The Implications of the Rise of AI/ML in the Cloud. In that article, I wrote about my expectation that the rapidly growing AI market will lead to the accelerated use of high-level synthesis (HLS), prototyping, and emulation. In this article, I will focus on the prototyping portion of that – specifically FPGA… Read More


Cadence Releases Enterprise-Level FPGA Prototyping

Cadence Releases Enterprise-Level FPGA Prototyping
by Bernard Murphy on 06-04-2019 at 5:00 am

Big prototyping hardware is essential to modern firmware and software development for pre-silicon, multi-billion gate hardware. For hardware verification it complements emulation, running fast enough for realistic testing on big software loads while still allowing fast-switch to emulation for more detailed debug where… Read More


ARM, NXP Share Usage, Challenges at Synopsys Lunch

ARM, NXP Share Usage, Challenges at Synopsys Lunch
by Bernard Murphy on 03-20-2019 at 7:00 am

Synopsys runs a “Industry verifies with Synopsys” lunch at each DVCon, which isn’t as cheesy as the title might suggest. The bulk of the lunch covers user presentations on their use of Synopsys tools which I find informative and quite open, sharing problems as much as successes. This year, Eamonn Quiqley, FPGA engineering manager… Read More