A very popular acronym is ‘WYSIWYG’ – What You See Is What You Get! This is very true and is important to visualize things to make it better in various aspects such as aesthetics, compactness, organization, structure, understandable for correction and so on; the most important, in case of semiconductor design, is being able to identify issues and resolve them to get the best PPA optimized design.
No matter how complex a design is, designers need to decompose it until the last bit and view the details in order to be able to debug it. At times, they need to shut other parts of design, simplify only the portion of interest and inspect it to correct things. Considering billion gate SoC designs today, it’s imaginable how difficult it would be to visualize these and correct. What if we have automated tools at various levels in the design process that can help designers visualize things in a matter of seconds to the level of details they need, and then analyze and correct?
Concept Engineeringhas such tools at transistor, gate, RTL and mixed-signal, mixed-language level that provide extremely easy visualization, analysis and debugging capability to designers, thus increasing their productivity. Besides, the company provides several other support utilities for designers as well as software components for EDA tool developers to delight designers’ experience; NlView[SUP]TM[/SUP] Widgets can be used for automatic schematic generation at transistor, gate, RTL, block and system level; optimized by algorithms and flexible to be controlled manually.
SpiceVision is a complete tool that reads Spice and works at the transistor and circuit component level and has numerous capabilities for viewing, analyzing, debugging, optimizing and documenting complete or part of the circuits at transistor level, thus speeding the overall circuit design. Parasitic level debugging which is considered tough can be made extremely easy by using SpiceVision.
GateVision is an ultra-fast gate level netlist viewer, analyzer and debugger, that can handle largest SoCs, process largest Verilog, LEF/DEF and EDIF netlists and display waveforms of simulation results with signal tracing up to the source level. High featured design navigation, logic cone extraction, interactive viewing, intuitive GUI etc. make the debugging activity fun for designers.
RTLvision provides fast viewing, debugging and optimizing capability for RTL code which can be written in VHDL, Verilog or SystemVerilog. It has several capabilities such as Clock Tree Extraction and interactive code navigation among others that make designers’ work easy.
StarVision is the ultimate in providing quick debugging capabilities to designers for mixed-signal, mixed-language designs, thus easing the job of integration of IPs from various sources into their complex SoCs. To make the job of analyzing and debugging complex SoCs (that can have its parts at different levels of abstraction) easy, StarVision works as an integrated cockpit that can be used to debug design at transistor, gate, RTL, or even source code level. Various parts of the designs can be analysed separately through various means.
Above is just a high level summary of these tools. To get what you want you get to see them personally. Concept Engineering is setting up a booth #11 at DATE[SUP]14[/SUP] (Design, Automation & Test in Europe) to be held in Dresden, Germany on 24-28 March 2014. Detailed presentations/demos of these capabilities will be provided along with latest tools and features.
There is another event in Silicon Valley on 24[SUP]th[/SUP] March, SNUG Silicon Valley Designer Community Expoat Santa Clara Convention Center, CA, at which Concept Engineering will showcase its products.
Meet the people who make the inside of electronic circuits visible to you!!