Stratus HLS (High Level Synthesis) Seminar Series [Part 2]: SystemC simulation and debugging

Stratus HLS (High Level Synthesis) Seminar Series [Part 2]: SystemC simulation and debugging
by Admin on 08-31-2023 at 2:05 pm

Date: September 15, 2023 (Friday) 15:00-16:00

Organizer:

Cadence Design Systems Japan
Innotech Co., Ltd. IC Solution Division

Cost: Free

Venue: Online (Zoom webinar)

* It is also possible to participate from a web browser.

We recommend using Google Chrome, Firefox, or Chromium Edge.

Registration deadline: September 14th

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Formal-based RISC-V processor verification gets deeper than simulation

Formal-based RISC-V processor verification gets deeper than simulation
by Don Dingee on 05-01-2023 at 10:00 am

End to end formal-based RISC-V processor verification flow for the Codasip L31

The flexibility of RISC-V processor IP allows much freedom to meet specific requirements – but it also opens the potential for many bugs created during the design process. Advanced processor features are especially prone to errors, increasing the difficulty and time needed for thorough verification. Born out of necessity, … Read More


Visual Debug for Formal Verification

Visual Debug for Formal Verification
by Steve Hoover on 04-20-2022 at 6:00 am

ThisIsFormal

Success with Open-Source Formal Verification

The dream of 100% confidence is compelling for silicon engineers. We all want that big red button to push that magically finds all of our bugs for us. Verification, after all, accounts for roughly two-thirds of logic design effort. Without that button, we have to create reference models,… Read More


Debugging in Conformal Low Power: GUI and Non-GUI Approach

Debugging in Conformal Low Power: GUI and Non-GUI Approach
by Admin on 10-07-2020 at 3:11 pm

Overview

Static low-power verification enables engineers to verify and debug multimillion-gate designs optimized for low power, without complex and time-consuming simulations. However, understanding these IEEE 1801 violations and diagnosing the root cause can become challenging without a user-friendly debug infrastructure.

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Up front phases improve CDC analysis

Up front phases improve CDC analysis
by Don Dingee on 09-19-2016 at 4:00 pm

Many tools find clock domain crossings (CDCs) in FPGA designs. Some don’t find the right ones since they don’t comprehend things like in-house synchronizer constructs. Some find too many based on misunderstanding intent, inaccurate constraints, and other factors that lead to noise.… Read More


More on HAPS hybrid prototyping for ARMv8 with Linaro

More on HAPS hybrid prototyping for ARMv8 with Linaro
by Don Dingee on 08-19-2016 at 4:00 pm

A few weeks ago we previewed a Synopsys webinar describing how they are linking the ARM Juno Development Platform with the HAPS-80 and HAPS ProtoCompiler environment. I’ve had a look at the archived event and have some additional thoughts.… Read More


One FPGA synthesis flow for different IP types

One FPGA synthesis flow for different IP types
by Don Dingee on 05-06-2016 at 4:00 pm

Both Altera and Xilinx are innovative companies with robust ecosystems, right? It would be a terrible shame if you located the perfect FPGA IP block for a design, but couldn’t use it because it was in the “wrong” format for your preferred FPGA. What if there were a way around that?

There is a compelling argument to use each FPGA vendor’s… Read More


Tcl scripts and managing messages in ASIC & FPGA debug

Tcl scripts and managing messages in ASIC & FPGA debug
by Don Dingee on 04-27-2016 at 4:00 pm

Our previous Blue Pearl post looked at the breadth of contextual visualization capability in the GUI to speed up debug. Two other important aspects of the ASIC & FPGA pre-synthesis workflow are automating analysis with scripts and managing the stream of messages produced. Let’s look at these aspects… Read More