PCIe Webinar Banner
WP_Term Object
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 3956
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 3956
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0

A Tool Conceived With Designers’ Input and Developed from Scratch

A Tool Conceived With Designers’ Input and Developed from Scratch
by Pawan Fangaria on 03-12-2014 at 10:15 am

If we look at the past, most of the EDA tools in the semiconductor design space have originated from a designers’ need to do things faster. Regardless of whether it is design exploration, manual design, simulation, verification, optimization (Power Performance Area – PPA) and many other steps in the overall design flow. What matters most, is how fast is the overall design turnaround with all kinds of design closures such as functionality, timing, area and power. Many tools are lost in the middle of market dynamics of mergers and acquisitions. However, my close observation tells me that the tools which are conceptualized with expert designers’ participation and driven in collaboration with design houses are built to last. They cannot be victimized as long as they serve the larger purpose of the overall design flow.

Often we ignore when designers ask something audacious, looking at it as if they needed a ‘push-button’ solution. But, hey, just wait, if you do not provide it today, it will become a reality tomorrow, and you may be left behind. If I look at RTL sign-off at the top level of the design flow, it was at an infancy stage in pre-millennium; however, today, it appears in the main-stream design flow. Inspired by this thought, I met Siddharth Guha, Sr. Manager at Atrenta’sNoida office. Siddharth is an expert of power solutions for SpyGlass RTL Sign-off platform. He has worked on SpyGlass Power since the very early years of this millennium. It was a nice opportunity for me to learn the intricate details about this product, what went behind the creation of this product, and how best it serves the industry. Here is the conversation –

Q: Siddharth, I guess SpyGlass Power is a well known product in the semiconductor design community. So, instead of talking generally about the product, tell me something about how it was conceptualized and how did it start?

A: Power used to be an aspect looked at toward the end of the design flow. However, as design sizes and complexities started increasing and technology nodes continued shrinking, power analysis and optimization gained importance. Our initial customers were looking for a tool which could estimate and optimize power of the chip in advance, managing budgets accordingly. So, estimating and optimizing power at the RTL, in the beginning of the design flow, was conceived with our customers’ inputs. This product was developed from the ground up, with intense customer participation at all stages of development; from conceptualization, to development, and including validation. Today it is effectively being used in production by our customers.

Q: What are the typical challenges that need to be handled by SpyGlass Power at the RTL?

A: Power closure with silicon is always a challenge. We have to make sure that the power stays within limits at every stage: RTL design, logic synthesis, pre-CTS, post-CTS and so on. Around 28nm and below, other issues that were not talked about earlier have become much more pronounced. For instance, for internal power, the accurate slew rate has to be taken into account, and the wire loads models are weak. Additionally, leakage power is very significant at smaller geometries. All these issues require the tool to estimate and reduce power as early as RTL.

Q: So, how does SpyGlass Power tackle these issues because many of these may show up late in the design cycle?

A: SpyGlass is a platform for the complete design flow. SpyGlass Power estimates power at the RTL as well as at the gate level which allows the user to track correlation of the power throughout the flow. Accuracy is achieved through calibration of reference gate level data or directly with technology found in SpyGlass Physical.

Q: That’s right, but looping back from physical (gate) level will take longer?

A: Yes, however, this looping is much less costly than traditional looping. What has to be looked at is how fast the designer gets the data to make right decisions. Since much of the design process starts early at RTL, things keep getting structured as we go down to layout level and refinements keep taking place at every stage so that we have no major surprises at the end of the design cycle. In the SpyGlass RTL Signoff platform, most of the tools are connected together which helps in faster convergence of the design.

Q: What are the major differentiating factors in SpyGlass Power?

A: SpyGlass Power provides a consistent and comprehensive solution for power estimation, reduction and verification. Our customers tell us that our best-in-class estimation engine provides faster results and convenient calibration with reference gate-level netlists. After power estimation, our users perform power profiling to check the quality of simulation data and the power efficiency of the current design. The profiling provides complete activity report with power computations. The power reduction step offers guidance to designers for possible power reduction through various means such as clock gating optimization, more efficient memory data operation for example. With the designers’ permission, SpyGlass Power can also fix the RTL for power reduction ensuring correct functionality with our SEC (Sequential Equivalence Checker). The power reduction engine also leverages SpyGlass CDC to ensure that the modified design is CDC safe. The power verification, SpyGlass Power checks the complete design against the power intent for various domains, level shifters’ states, isolation logic etc. As our customers tell us, SpyGlass Power provides a complete solution for power from architecture to estimation, reduction, auto power fix, and verification at all levels.

Q: So, how do you see customer response to SpyGlass Power?

A: Our customers are very happily using this tool. We work in a very collaborative manner and take a pro-active approach in solving the issues designers face. We have seen our customers using this tool in unique ways, which we had not envisioned while developing the tool. For example, while using this tool for chip power optimization, they also use the activity report to improve their software and optimize transactions on the design.

Q: That’s quite heartening. What more are designers looking forward to, from this tool, for their large SoC designs?

A: Interesting question. Although SpyGlass Power supports UPF, one of our customers recently requested that it should leverage a set of specific constructs that would allow the tool to model the effect of automatic switching and voltage scaling of power domains. Looking at the huge number of these domains in today’s SoCs, this is going to be fun challenge to achieve.

It was a great session with Siddharth for me to learn about what goes into the making of SpyGlass Power. It definitely looks to be an effective tool that provides large returns for the designers’ time. Since power has become more important, not only for mobile and hand held devices, but also for other consumer and home appliances, I can see a rising demand for such a tool in the semiconductor design community.

More Articles by Pawan Fangaria…..

lang: en_US

Share this post via:


There are no comments yet.

You must register or log in to view/post comments.