Power Analysis in Advanced SoCs. A Siemens EDA Perspective

Power Analysis in Advanced SoCs. A Siemens EDA Perspective
by Bernard Murphy on 02-23-2022 at 6:00 am

Power verification methods min

The success of modern battery-powered products depends as much on useful operating time between charges as on functionality. FinFET process technologies overtook earlier planar CMOS in part because they significantly reduce leakage power. But they exacerbate dynamic power consumption thanks to increased pin capacitances.… Read More


Webinar: System Level Modeling and Analysis of Processors and SoC Designs

Webinar: System Level Modeling and Analysis of Processors and SoC Designs
by Daniel Payne on 05-10-2021 at 10:00 am

exploration flow min

Engineers love to optimize their designs, but that implies that there are models and stimulus to automate the process.  Process engineers have TCAD tools, circuit designers have SPICE for circuit simulation, logic designers have gate-level simulators, RTL designers use logic simulation, but what is there for the system architects… Read More


Clock Gating Optimization

Clock Gating Optimization
by Bernard Murphy on 09-21-2017 at 7:00 am

You can save a lot of power in a design by gating clocks. For much of the time in a complex multi-function design, many (often most) of the clocks are toggling registers whose input values aren’t changing. Which means that those toggles are changing nothing functionally yet they are still burning power. Why not turn off those clock… Read More


Webinar: Getting to Accurate Power Estimates Earlier and Faster

Webinar: Getting to Accurate Power Estimates Earlier and Faster
by Bernard Murphy on 05-24-2017 at 7:00 am

Power has become a very important metric in modern designs – for mobile and IoT devices which must live on a battery charge for days or years, for datacenters where power costs can be as significant as capital costs, and for increasingly unavoidable regulatory reasons. But accurate power estimation on a design must start from an … Read More


System-Level Power Estimation

System-Level Power Estimation
by Bernard Murphy on 05-09-2017 at 7:00 am

When I first saw that Rob Knoth (Product Director at Cadence) had proposed this topic as a subject for a blog, my reaction was “well, how accurate can that be?” I’ve been around the power business for a while, so I should know better. It’s interesting that I jumped straight to that one metric for QoR; I suspect many others will do the same.… Read More


A Credible Player at the Power Table

A Credible Player at the Power Table
by Bernard Murphy on 08-03-2016 at 7:00 am

For a while it seemed like Mentor lived on the margins of the (RTL) design-for-power game. They had interesting micro-architectural optimization capabilities through their Calypto heritage but no real industry chops in power estimation, a must-have when you are claiming to reduce power. Better known offerings in RTL power … Read More


Palladium Moves Power (and Temperature) Modeling to the System Level

Palladium Moves Power (and Temperature) Modeling to the System Level
by Bernard Murphy on 12-13-2015 at 12:00 pm

I had a debate with Steve Carlson of Cadence earlier in the year at the EDPS conference on whether there were really any truly effective solutions for doing power estimation in emulation. I thought there weren’t and he said I was wrong. After attending the Cadence front-end summit last week, I have to admit he has a point.

First, who… Read More


Cadence Enters the RTL Power Estimation Game

Cadence Enters the RTL Power Estimation Game
by Bernard Murphy on 12-09-2015 at 12:00 pm

At the Cadence front-end summit last week, Jay Roy presented the Cadence Joules solution for RTL (and gate-level) power estimation. Jay is ex-Apache, so knows his way around RTL power estimation which should make Joules a product to watch. Joules connects very natively to Palladium for power characterization for realistic software… Read More


A Tool Conceived With Designers’ Input and Developed from Scratch

A Tool Conceived With Designers’ Input and Developed from Scratch
by Pawan Fangaria on 03-12-2014 at 10:15 am

If we look at the past, most of the EDA tools in the semiconductor design space have originated from a designers’ need to do things faster. Regardless of whether it is design exploration, manual design, simulation, verification, optimization (Power Performance Area – PPA) and many other steps in the overall design flow.… Read More