Most programmers can read a code snippet and spot errors, given enough hours in the day, sufficient caffeine, and the right lens prescription. As lines of code run rampant, with more unfamiliar third-party code in the mix, interprocedural and data flow issues become more important – and harder to spot.
Verification IP particularly resembles that third-party code remark: vendors supplying UVM for test is now widely-accepted practice. Debugging a large testbench environment with a lot of third-party UVM can become a rather hilatious effort if the only view available is a text error message, likely launched somewhere in the middle of potentially foreign code not being fed something it expects. Tracking down dependencies in the midst of the model from just the source code view is possible, but slow going.
The latest release of Aldec Riviera-PRO 2014.02 brings a powerful new feature to testbench debugging: UVM Graph. Integrated directly into the tool on a new tab, UVM Graph lets users switch from their UVM source code view into a top-down visualization showing the components and objects and transaction-level modeling (TLM) connections between them.
Clicking a component rectangle expands its contents showing the encapsulated objects with ports and interfaces, quickly revealing exact details of the testbench model. A right click takes you to a cross-probe window for a closer look at objects or classes, or back to the source itself. Icons next to object names show their types.
For another perspective on the UVM Graph capability, an Aldec guest blog post from Srinivasan Venkataramanan of CVC shares his first look at the tool:
The new Riviera-PRO 2014.02 release doesn’t stop there. Another new feature is a Finite State Machine (FSM) window, with a color-coded graph showing state transitions. The same data can also be presented in a tabular format, handy for highlighting transition counts.
We explored Riviera-PRO’s plotting capability in a previous release about a year ago, and this latest release includes a significant enhancement. Plots are great at viewing data quickly, but in a large data set even a plot can be overwhelming. Setting limits gives users control over what is seen and can improve readability for many situations.
Per normal, Aldec continues to make incremental improvements in Riviera-PRO, speeding up SystemVerilog simulation and GUI viewing performance at each release. Riviera-PRO uses Flexera Software FlexNet Publisher for licensing, with an update in this release that preserves existing licenses but uses the latest licensing daemon. For an overview of all the improvements, download the updated Riviera-PRO What’s New presentation.
Testbench software productivity today means bringing new in-house and third-party code into the mix quickly, and avoiding the need to read through code manually. The ability to visualize code and the relationships between code modules is a huge debugging aid, and the addition of UVM Graph to Aldec Riviera-PRO should be a welcome improvement for those working in UVM on a daily basis, or those new to the arena.