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DSP running 10 times faster at ultra-low voltage?

DSP running 10 times faster at ultra-low voltage?
by Eric Esteve on 03-11-2014 at 12:30 pm

The LETI and STMicro have demonstrated a DSP that can hit 500 MHz while pulling just 460mV – that’s ten times better than anything the industry’s seen so far. Implemented on a 28nm FD-SOI technology, with ultra thin forward body biasing (UTFBB) capability (used to decrease Vth), this DSP can also be exercised at higher voltage when required by the application, then hit 2.6 GHz at Vdd = 1.3 V, equivalent to a similar device implemented on a 22nm Tri-gate technology (2.5 GHz at 1.1 V). But, for any mobile application, delivering 500 Mops at 460 mV is a big achievement: according with Fabien Clermidy, head of Digital Design and Architecture at Leti, this could mean extending your battery life by about another 30% for typical usages. Leti and ST showed the FD-SOI DSP at ISSCC – the IEEE’s International Solid-State Circuits Conference (February 2014), which is widely considered the premier forum for presenting advances in solid-state circuits and SOCs.

As you can see on the above picture, the Forward bias capability is the key enabler of such a performance at ultra-low voltage level: even if we would have to zoom the picture in the 400-500 mV abscise, it’s the 2000 mV FBB Boost that allows reaching the 500 MHz bar, as with no FBB Boost, the DSP would run in the low 100’s MHz range. Such a result is already a great achievement, but we can analyze another advantage of using FDSOI technology: to reach the maximum DSP performance, 2.6 GHz in this work, a chip maker would have to target a more expansive technology, the Tri-gate 22 nm.

In this table, we see that the maximum frequency is reached with work (1) and (4), or 2.6 GHz at 1.3V Vdd on 28nm UTBB FD-SOI and 2.5 GHz at 1.1V Vdd on 22nm Trigate. From the previous articles about FDSOI, you know that the over-cost of SOI wafers is more than compensated by the exploding fabrication cost increase paid by going further by one technology node, then the over-cost related to Trigate implementation compared with planar transistor used for FDSOI in this work. That is, the DSP described by the LETI/STM paper presented at ISSCC can exhibit TWO advantages when compared with a 22 nm Trigate:

  • End user can benefit from a 30% reduction of the power consumption, when the DSP runs at ultra-low voltage (460 mV), still delivering 500 MHz performance
  • The same device can deliver same performance than 22nm trigate (2.5 or 2.6 GHz), at a much lower cost

The later is interesting too, as the semiconductor industry is facing a BIG economic issue: Moore’s law has been empirically defined by Gordon Moore, as an economic law (back-up by simple maths, not by physics), saying that the cost per gate was divided by two every 18 months. That we see, starting with 20 nm technology node, is now a cost increase node after node. The reasons why this cost per gate is increasing have to see with the laws of physics: don’t forget that 20 nm is half of the smallest visible wavelength, for example! Nevertheless, there will be applications where integrating more IP (CPU, GPU, DSP, SRAM etc.) into a SoC, or designing the most performing CPU, or an ultra-low power device to stay competitive will justify paying a price premium, not only a price per gate, but also a huge increase of development cost. But how many fabless chip makers will be able to invest so much, or, if you prefer, how many market segments will economically justify making such an investment?It’s good to know that technologies like FD-SOI will allow continuing Moore’s law, and I will come back with more explanations and material in the very near future to illustrate this assumption…

From Eric Esteve from IPNEST

More Articles by Eric Esteve…..

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