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UTBB SOI can scale down to 5nm says Skotnicki…

UTBB SOI can scale down to 5nm says Skotnicki…
by Eric Esteve on 07-29-2015 at 12:00 am

…and FinFET down to 3nm. This assertion is the result of extensive research work made by Thomas Skotnicki, ST Fellow and Technical VP, Disruptive Technologies, leading to numerous publications, like in 1988 in IEEE EDL or in 2008 in IEEE TED paper. I say extensive, I should also say long, very long, as it took almost 30 years for the industry to recognize that, finally, such FD-SOI devices may compete with Bulk and FinFET. A good illustration is the fact that ST has first developed FD-SOI 28nm technology in 2011, followed by Samsung licensing the technology in 2014, then GlobalFoundries licensing the 22nm FD-SOI in 2015… and ST offering now 14nm FD-SOI.

Why does planar transistor fail for technology node below 20nm? The answer is Short Channel Effect (SCE) and Drain Induced Barrier Lowering (DIBL) is the short channel effect with the higher impact: in short-channel devices the drain is close enough to gate the channel, and so a high drain voltage can open the bottleneck and turn on the transistor prematurely. If you look at the three left devices, Bulk, PD-SOI and Thick Box SOI, you can see that the theory predict a minimum effective gate length in the 30nm range. Effective gate length (Lel) is commonly used to name a technology node (ie: 40nm, 28nm, etc.) and preferred to the designed gate length for marketing reason as it’s lower and sounds more aggressive. DIBL for the Bulk device is calculated by Skotnicki and DIBL = 140 mV; the threshold voltage is lowered by 140 mV.

If planar transistor fails, the industry needs to find new CMOS technologies in order to develop smaller geometry devices, the only way to benefit from faster and lower power transistors (I didn’t say cheaper) leading to design higher performance circuits. At this point, you may think that if Silicon CMOS is reaching physical limit, why not using completely different device technology, based on III-V material for example. We know that GaAs (Gallium Arsenide) exhibit electron mobility much higher than the Silicon: 8500 compared to 1400 cm2/V.s. Why not designing processor on GaAs, theoretically running at 15 GHz when the same on Silicon would be limited at 2.5 GHz?

The answer is oxidation: if you take a raw pure Silicon wafer and put it in a room, a SiO2 layer will naturally grow on the wafer. Obviously you will grow Silicon oxide by using much more sophisticated techniques in a fab, and you do it several times to eventually output the desired IC. Now take a raw GaAs wafer and try to grow oxide on it: the (defunct) Laboratoire Electronique de Philips (LEP) has spent multi-million dollar and many years trying to do it in the 80’s, and never succeed. I know it because I was working in LEP in 1983 and I still remember that it was the first priority for this research center. With no native oxide you will never be able to build GaAs based IC as complex as it can be in Si CMOS, at least at a reasonable cost. Let’s come back to Silicon.

If you look now at the three boxes on the right side, you see that the limit for Ultra Thin Body and Box (UTBB) SOI is now 7nm, going down to 5nm for “Ultimate UTBB SOI” and 3nm for FinFET. UTBB implies using 5nm Box thickness, the height of the oxide layer deposited on the raw Silicon wafer (SOITEC is the supplier of such SOI wafers). Ultimate UTBB define a kind of theoretical limit for FD-SOI as the oxide thickness (on the wafer) has to be the same than the gate oxide value or very, very thin. The FinFET technology leads the pack, with a theoretical limit at 3nm, and we will see why it’s not a surprise (at least for Skotnicki, to be honest it was a surprise for me) by looking at the next picture.

On the left side we start with the UTBB FD-SOI model. In blue, the bulk silicon, in yellow the oxide deposited on the bulk and in pink the source and drain of the transistor. Then in yellow again the gate oxide and the gate itself on the top of this thin oxide layer. If you manipulate this active structure as indicated by the three intermediate pictures, the final device is becoming… a FinFET. I agree that this manipulation require some imagination and also some ability for theoretical 3D visioning, but it’s interesting to notice that the two emerging technologies allowing overcoming the issues linked with the planar transistor are sisters.

At this point, you may think that this theoretical demonstration made by Skotnicki is superb, but is it production proven or will it stay a paper work? Better than a long talk, the answer is in the above picture. On the left side you see a 28nm FD-SOI devices (Gate length = 25nm = Box height) which is production proven as ST has processed ASIC for both internal use and customers in this technology. The blue arrow is an illustration of FD-SOI roadmap to 10nm (or maybe 14nm as a marketing label), it may be issued from a pilot fab, but it will certainly end in production.

Encore Bravo, Mr Skotnicki!

This post has been written from “The Success Story of FD-SOI – From Equation to Fabrication” presentation given by Thomas Skotnicki during the FD-SOI Workshop, the LETI days, June 2015.

From Eric Esteve from IPNEST

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