WP_Term Object
    [term_id] => 31
    [name] => GlobalFoundries
    [slug] => globalfoundries
    [term_group] => 0
    [term_taxonomy_id] => 31
    [taxonomy] => category
    [description] => 
    [parent] => 158
    [count] => 218
    [filter] => raw
    [cat_ID] => 31
    [category_count] => 218
    [category_description] => 
    [cat_name] => GlobalFoundries
    [category_nicename] => globalfoundries
    [category_parent] => 158
    [is_post] => 1

In the Valley & thinking about FD-SOI for your next chip design? Epic (and free) symposium 13 April

In the Valley & thinking about FD-SOI for your next chip design? Epic (and free) symposium 13 April
by Adele Hars on 04-02-2016 at 7:00 am

If you’re in the chip biz in Silicon Valley, check out the SOI Consortium FD-SOI Symposium on April 13th in San Jose. They’ve been running these things since 2009, and I have to say that this one is the most comprehensive to date. Headliners include Cisco, Sony, NXP, SigmaDesigns, ARM, Ciena plus the big FD-SOI foundries, EDA companies, design partners, chipmakers and analysts. There is a special session dedicated to RF and analog design innovation on FD-SOI with STMicroelectronics, Stanford and others. In short, we’re going to get a chance to the see FD-SOI ecosystem in action.

To attend, all you have to do is register in advance – click here to go to the registration page. It’s free and open to everyone who registers.

It’s really a terrific agenda – check it out:

08:00AM – 09:00AM – Registration
08:55AM – 09:00AM – Welcome by Carlos Mazure, SOI Consortium
09:00AM – 09:30AM – Aglaia Kong, Cisco Systems, CTO for Internet of Everything
09:30AM – 10:00AM – Thinh Tran, Sigma Designs, CEO
10:00AM – 10:30AM – Ron Martino, NXP, VP, Application Processors & Advanced Technology Adoption
10:30AM– 10:50AM– Coffee Break
10:50AM – 11:20AM – Subramani Kengeri, GLOBALFOUNDRIES, VP CMOS Business Unit
11:20AM – 11:50AM – Will Abbey, ARM, GM Physical IP
11:50AM – 12:20PM – Kelvin Low, Samsung Semiconductor, Senior Director, Foundry Marketing
12:20PM – 1:40PM Lunch
1:40PM – 2:10PM – Kenichi Nakano, SONY, Sr. Manager, Analog LSI Business Division
2:10PM – 2:40PM – Dan Hutcheson, VLSI Research, CEO
2:40PM – 3:05PM – Mahesh Tirupattur, Analog Bits, EVP
3:05PM – 3:30PM – Mike McAweeney, Synopsys, Sr. Director, IP Division
3:30PM – 4:00PM – Coffee Break
4:00PM – 4:30PM – Naim Ben-Hamida, Ciena, Senior Manager
4:30PM – 4:55PM – Rod Metcalfe, Cadence, Group Director, Product Engineering
4:55PM – 5:20PM – Prof. Boris Murmann, Stanford, on “Mixed-Signal Design Innovations in FD-SOI Technology”
5:20PM – 5:45PM – Frederic Paillardet, STMicroelectronics, Sr. Director, RF R&D
5:45PM – 6:00PM – Ali Erdengiz, CEA-LETI, Silicon Impulse
6:00PM – 6:05PM – Closing remarks by Giorgio Cesana, SOI Consortium

Seriously – this good. Plus during breaks there will be poster sessions with GSS, sureCore, Soitec, SEH and the SOI Consortium.

Please note that if you’ve already registered last month when the first announcement went out, the location has changed. The SOI Consortium FD-SOI Symposium will be held on Wednesday, 13 April 2016, from 8am to 6:30pm at the:Doubletree Hotel San Jose
2050 Gateway Place
San Jose, California 95110, USA

If you can’t make it, not to worry – I’ll be there taking notes for a round-up and follow-up articles. Plus I’ll be doing plenty of tweeting and retweeting (follow me @AdeleHars – look for the hashtag #FDSOI). And of course you’ll want to follow the Twitter feeds of participating companies, and of the SOI Consortium @SOIConsortium.org.

 Most of the presentations will also be available on the SOI Consortium website following the event. In the meantime, you can click here to peruse the presentations from previous events.