I recently took a look at the current status and future direction of FinFET based logic processes in my Leading Edge Logic Landscape blog. I thought it would be interesting to take a similar look at FDSOI and to compare and contrast the two processes. My Leading Edge Logic Landscape blog is available here.
As a reminder from the Leading Edge Logic Landscape blog, I will be using a formula developed by ASML to take my pitch projections and turn them into “Standard Nodes” for comparison purposes (the formula is described in the leading edge blog).
ST has been a champion of FDSOI technology for a long time and introduced a 28nm FDSOI process in 2014 that they developed with Leti. ST along with Leti have also developed a 14nm FDSOI process but we don’t believe they are running it. Their FDSOI wafers are fabricated at their Crolles II – 300mm wafer fab. Crolles II was originally a three company development fab but is now solely an ST fab and has been scaled up over the years. Still Crolles II is a relatively small 300mm fab with approximately 21,000 wafers per month (wpm) capacity and is also fairly old having come on-line in 2002. Recently there has been some speculation that Crolles II may be closed down calling into question whether ST will continue to produce FDSOI internally.
Samsung has licensed ST’s 28nm FDSOI platform and is offering the process as their 28FDS process. The 28FDS process is currently ramping up. Samsung has also discussed a follow on FDSOI process, but our understanding is they will avoid multi-pattering so it will likely be a relaxed 22nm process (we will refer to is as 22FDS).
Leti is a development organization that pioneered FDSOI development 15 years ago. Along with ST, Leti has developed 28nm and 14nm technologies, they are also working with GF on the 22FDX and 12FDX platforms (see the next section). Leti has run some test devices on a 10nm FDSOI technology and done modeling on 10nm and 7nm FDSOI. They believe FDSOI can scale down to 7nm.
I have written a blog about Leti’s FDSOI technology that is available here.
GF has a 22nm FDSOI process (22FDX) with risk production in Q1-2017 in their Dresden fab and they recently announced a 12nm FDSOI technology (12FDX) due out in 2019. GF has the most aggressive FDSOI program with the longest roadmap and a strong commitment to capacity with their Dresden fab. FDSOI is basically the path forward for the Dresden fab and the fab has a current capacity of approximately 60,000 wafers per month with some room for expansion.
Using the Standard Node formula previously discussed we can now compare standard nodes by node name and year for the three companies pursuing FDSOI.
The first table presents the “standard nodes’ versus the company node names based on our projections of pitches for each process.
The second table presents the standard node versus year for the three FDSOI producers and also presents the standard node versus year for the densest FinFET technology available each year.
From the second table we can see that GF is clearly the FDSOI process density leader. We can also see that FinFETs have a much higher density than FDSOI (currently ~2x) and the density advantage is expected to grow over time (~3x in 2019). We will discuss the significance of this further below.
FDSOI versus FinFETs
There is a lot of discussion that goes on around FDSOI and FinFETs and which one is the “better” technology, in my opinion this is entirely dependent on the application. In this section we will cover the strengths and weaknesses of each technology.
[*=left]Wafer Cost – Handel Jones has published a study claiming a cost advantage for 14nm FDSOI over 16nm FinFETs. The study claims that FDSOI will have a lower wafer cost and a higher yield. My company, IC Knowledge LLC is the world leader in cost modeling of semiconductors and MEMS. I have modeled TSMC’s 16FF+ process versus a 14nm FDSOI process based on ST’s published 14nm process flow, and for the same number of metal layers in the same fab, I find nearly identical wafer costs. In addition to this TSMC has now introduced 16FFC with a reported 8 to 10 less masks than 16FF+. 16FFC would have a significant wafer cost advantage over 14nm FDSOI. Where FDSOI will have a wafer cost advantage is in situations where 22FDX can be used in place of a 16nm/14nm FinFET process or 12FDX in place of a 10nm FinFET process.
[*=left]Yield – when a new process is introduced, yields are low and then over time the yields improve as the process matures. There is a belief held by some people today that FinFETs are intrinsically low yielding, when in fact Intel’s 22nm FinFET process is their highest yielding process ever! Intel has struggled to ramp up the yield of their 14nm process but we believe this is due to the aggressive pitches of the process and today the 14nm process has yields similar to their 22nm process. GF, Samsung and TSMC are all reporting excellent yields on their 16nm/14nm processes. With 16nm/14nm FinFET processes in production since 2014, it is hard to imagine a process that won’t be introduced for several more years having yields even as good as the mature FinFET yields for an extended period of time.
[*=left]Gate Density – from the Standard Node Versus Year table it can be seen that FinFETs have and will maintain a significant gate density advantage over FDSOI. Even at the same “node” FinFETs are poised to have a gate density advantage. If wafer costs and yields are similar, the FinFET gate density advantage would result in lower cost per gate. With cost reduced FinFET processes providing lower wafer costs, FinFET yields likely to be higher for an extended period of time and gate densities higher, FinFETs should provide the lowest cost per digital gate.
[*=left]Design Cost – design cost is an area where the simpler FDSOI processes have a significant advantage. It is estimated that a 16nm/14nm FinFET design is >2x the cost of a 28nm planer design. 10nm and 7nm FinFET processes are expected to be significantly worse. The GF 8 metal 22FDX process is reported to have design costs similar to 28nm planar. This is a really big advantage for designs that run in mid to low volume.
[*=left]Power – most FinFET processes run at around 0.8 volts (TSMC 16FFC can run down to 0.55 volts). The GF 22FDX process can run down to 0.4 volts and the 12FDX process is expected to run at <0.4 volts giving the FDSOI processes a significant active power consumption advantage. This is very important for battery powered applications.
[*=left]Drive Current – for very large designs (large area chips) requiring the highest possible performance, drive current is critical and FinFETs have higher drive current than FDSOI.
[*=left]Analog – FDSOI provides good analog performance and allows designers to size transistors as needed whereas in FinFET designs sizing is in increments of Fins. Planar devices such as the FDSOI devices also have lower parasitic capacitance.
[*=left]RF – the GF 22FDX process has demonstrated an f[SUB]MAX[/SUB] of >300GHz versus ~150GHz for their 14LPP FinFET process. RF circuits require devices with approximately 6x the f[SUB]MAX[/SUB]of the operating frequency and FDSOI can meet the requirements of 5G and millimeter wave.
[*=left]Body Biasing – FDSOI enables body biasing of transistor that can be used to actively tune the transistors for performance or low power. This is a useful feature and is unique to FDSOI.
From the bullet points above it can be seen that FinFETs and FDSOI each have their advantages. FDSOI has lower design cost, lower active power, and better analog and RF performance. FinFETs have better gate density and drive current. Which process type is optimal will depend on the specific requirements of an application.
Today FDSOI is just getting started as a technology and we estimate that less than 10,000 wpm of FDSOI are being run worldwide (in contrast to several hundred thousand wpm for FinFETs). As Samsung ramps up 28FDS and GF Ramps up 22FDX we expect to see a number of low power – small to mid-complexity designs often with analog and RF introduced on FDSOI, and FDSOI to begin to capture market share. FDSOI may even capture some low to mid performance cell phone processor applications and is clearly well positioned for Internet of Things (IOT) and 5G. 28FDS, 22FDS and 22FDX offer a low cost migration path for older 40nm and 28nm bulk planar designs. 22FDX and 12FDX can also offer lower cost alternatives to 16nm/14nm and 10nm FinFET processes where lower digital performance and density can be tolerated in exchange for lower design costs and better analog and RF performance.
FinFETs already well established in the market will continue to evolve and improve with lower costs, higher gate densities and improving performance. We expect high end cell phone applications processors, PC processors, FPGAs, high end graphics processors, network processors and other large – high performance – high volume designs to continue to be produced with leading edge FinFET processes. Cloud based servers, virtual reality and possibly self-driving car applications should continue to drive high end FinFET usage (although FDSOI will also be useful for automotive applications).