Recently, TSMC conducted their annual Open Innovation Platform forum meeting in San Jose. Although TSMC typically eschews a theme for the forum, David Keller, EVT TSMC North America, used a phrase in his opening remarks that served as a foundation for the rest of the meeting – “celebrate the way we collaborate”.
The forum begins with a technology overview session from TSMC. Jack Sun, VP and CTO TSMC R&D, provided the keynote, entitled: ”Technology Leadership for Collaborative Innovation”. Cliff Hou, VP R&D Design Technology Platform, provided an update on the design flow enablement and IP readiness for TSMC’s advanced process nodes.
Their presentations were followed by 3 tracks of customer and EDA vendor presentations, highlighting areas where their collaboration with TSMC has resulted in pushing the envelope of new designs and design methods.
The following list highlights five key impressions from the forum, mostly related to TSMC’s roadmap update. (I should note that there are subjective comments included, which solely represent my opinions, not those of TSMC.)
(5) Platforms: End-market requirements are driving broader design enablement releases
TSMC has adopted a design enablement strategy with 4 platforms, to address unique characteristics of key market segments. Customers will be incorporating the associated PDK models, techfiles and reference flows for their specific market. (Clearly, this strategy entails much greater support from Cliff’s team.) The four platforms are:
a) High Performance Computing platform
The majority of the HPC platform discussion pertained to the 7nm node.
Characteristics of device models and tool qualification include:
- FEOL device models need to support VDD overdrive and hyper-overdrive performance boost modes
- BEOL interconnect design rules use wider upper level metals, larger vias
- TSMC is providing an “H360” standard cell foundation IP library
- power-grid construction flows focus on minimizing IR, addressing EM issues
- clock-tree synthesis must meet very low skew requirements
- improved wiring delay optimization will be needed in APR flows
- statistical timing analysis support is required
- statistical EM analysis is required
b) Mobile platform
As with HPC, the focus was on the availability of the 16FFC platform, and the development underway for the upcoming 7nm node. Relative to N10FF, the 7nm mobile platform offering offers improvements of ~15% performance (iso-power), ~35% power (iso-performance), with a gate density improvement of 1.65X.
- TSMC is providing an H240 standard cell dense library, for maximal gate density
- Similar EDA reference flow requirements as the HPC platform
c) Automotive platform
Clearly, there is an expectation for a growing market for automotive electronics, to address a growing set of ADAS feature requirements, as guided by the ISO-26262 standard.
The TSMC automotive platform is currently focused on the N16FFC process node, with PDK support for extended operating environment conditions:
- models qualified to 150 degrees C (from 125 C for HPC)
- EM model analysis to 125 C, statistical EM sign-off
- TSMC IP qualification reports provided for NBTI, PBTI, HCI, TDDB, device aging
- SRAM soft error model enhancements
d) IoT platform
TSMC is working on ensuring Ultra Low Power PDK support across a wide set of process nodes, focusing on IP qualification at lower operating voltages – i.e., 40ULP (1.2V à 0.9V), 28HPC (0.9V à 0.7V), 16FFC (0.8V à 0.55V).
An extra-high Vt device offering (EVHT) adds to the available set of Vt targets. A low-leakage SRAM bitcell IP is also available.
TSMC expressed support for working with customers on near Vt characterization, as well.
4) High capacity memory array technology alternatives in R&D
Jack S. briefly alluded to the R&D activity underway to investigate alternative memory array technologies, specifically embedded Resistive RAM (eRRAM) and embedded Magnetoresistive RAM (eMRAM). Yet, no specific timeline for process node introduction was provided.
This is in contrast to announcement from other foundries, which have provided (preliminary) dates for eMRAM introduction. I found this distinction to be interesting.
3) N10, N7 development “on track”
TSMC shared dates for N10 and N7 production availability. N10FF will ramp this year. The very aggressive N7FF schedule (for HPC and mobile platforms) is an extremely impressive feat.
Reference flow support for the 7nm EDA features listed above will be available in 4Q’16.
N7FF foundation and SRAM IP will be available to the v0.5 PDK release this year.
Risk production tapeouts will be accepted in 1Q’17. High-speed SerDes IP will be available to the v1.0 PDK in 2Q’17.
This is especially impressive, given the additional design enablement resource required for the two platforms – with different design rules, PDK models, standard cell IP, etc.
2) DRC waivers at 7nm? Fuhggedaboudit…
One of the indirect benefits of attending the TSMC OIP forum is the opportunity to chat with TSMC’s EDA and IP partners at their booths. Another is the chance to network with TSMC customers over lunch and coffee breaks. I ran into a colleague from years past, who shared an insight that has since stuck with me.
His contention (not necessarily TSMC’s) was that: “Design rules at 7nm, with 193i photolithography, require a new way of thinking. Design rules are strict. In essence, TSMC is confirming ‘We can print this with these rules, but don’t expect any significant process latitude.’ The days where a custom designer could approach TSMC with a request for a tapeout DRC waiver to realize a PPA benefit for a specific set of cells are long gone.”
He further commented, “At 7nm, I wouldn’t consider any IP that hasn’t been proven in silicon. I’d like to see the IP tapeout signoff review data, and the post-silicon characterization reports. There’s simply no layout design margin anymore.”
Those comments really resonated with me.
1) new 7nm requirement, with a significant tool/flow impact
Each new technology brings new challenges – the exciting nature of our industry is how those challenges are solved. N7FF introduces a unique requirement.
Throughout the scaling of process nodes, interconnect resistance per unit length and via resistance have increased. FinFET’s provided an increase in the areal current density. For high performance designs, the scaling of interconnects strongly impact both interconnect delays and electromigration reliability. For long routes, the goal is to promote signals to higher (thicker) levels of metallization for optimal timing. For EM robustness, the goal is to provide sufficient metal for the associated current density, an issue that is of specific concern at the output of a FinFET cell (through an output pin).
The photolithographic limitations at 7nm preclude traditional methods to address these issues, such as large via bars on dog-bone metal ends. Instead, via pillars will be required, with a significant impact on routing track resources.
A presentation from Synopsys highlighted the extent to which the insertion of via pillars as part of both timing and EM optimization has influenced tools and design methods. The full set of synthesis and implementation flows from Design Compiler-Graphical through IC Compiler-II APR has to be adapted to the via pillar design style. Clock-tree synthesis and optimization involves inserting buffers and optimal pillars to balance loading. Signal routing and post-route optimizations are strongly impacted, as you might imagine. The promotion/demotion of route layers for optimization has to include the congestion impact of associated pillars. All these optimization algorithms rely upon accurate parasitic extraction of the pillar structure.
In summary, the TSMC OIP forum highlighted the collaboration needed among customers, EDA vendors, and the foundry, to enable design success at advanced nodes. And, the coming introduction of 7nm design enablement will include several challenges, necessitating pretty significant changes in design styles and methods. With every challenge comes an opportunity to pursue new innovations in our industry.
-chipguyShare this post via: