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FD-SOI: GlobalFoundries 22nm Update

FD-SOI: GlobalFoundries 22nm Update
by Paul McLellan on 08-26-2015 at 7:00 am

 As I said yesterday, last week was the GSA Analog/Mixed-Signal working group completely dedicated to FD-SOI. ST went first and had a presentation that was a mixture of an introduction to FD-SOI that I have covered times that are too numerous to mention.  Then they did a dive into analog and RF capabilities for FD-SOI that went very deep into two test projects, deeper than I could follow in detail (my PhD is in software not RF design). But the key is in the picture above. The pictures on the right show how back-biasing is actually applied. You apply a positive voltage to the back of the N transistors and a negative one to the back of the P. The graph on the left shows the result. The tiny red line shows how substrate bias works in a bulk process: you can only do a little and it isn’t very effective. The blue line is what you can get with FD-SOI biasing. Actually, since biasing can go to 3V I believe you can do even more. See also FD-SOI: Samsung Opens the Kimono a Little Last up was Jamie Schaeffer of GlobalFoundries. Their introductory slides on the motivation for FD-SOI were largely the same as ST and Samsung. But GF’s process is 22nm, what they call 22FDX. They had 3 reasons for doing 22nm rather than 28nm:

  • they have a big fab in Dresden that can do 22nm but can’t go to 14nm
  • 22nm doesn’t require double patterning (it is no coincidence that Intel’s first FinFET process was also 22nm)
  • they can address a bigger market with 22nm than 28nm

 They actually have several flavors of the process, to address slightly different markets at the cost of a couple of extra mask steps in most cases. See above for details but the 4 process options are:

  • ulp: ultra-low power
  • ull: ulra-low leakage
  • uhp: ultra-high performance
  • rfa: integrated RF and analog

 The 22FDX body biasing works the same as in 28nm (only more so). With FBB they can get low voltage operation down to 0.4V which is the lowest of any process in existence or that GF knows to be in development. With RBB they can get leakage down to 1pA/um. Those are both impressive numbers. There are also all the advantages in terms of being able to tune gain, linearity, noise immunity and more in analog/RF designs.  There are also multiple transistor types which allow you, as you would expect, to get different power/performance points. With FBB and RBB each of these transistors can hit multiple points. See the above diagram for more details.  These transistors can all be mixed on the same die. So for an IoT device you can imagine having a little watchdog processor waiting for something to happen: a button press, a timer expires, motion is detected. This can use RBB for the lowest possible leakage. The assumption is that the watchdog does not need much performance, although that can depend on the activity obviously. That can then wake up the comms processor that has integrated RF. Finally a power hungry image processor is awoken using FBB and fast transistors to analyze the scene and zoom on on the area of interest. Then everyone goes back to sleep except the watchdog. The bias gives you a lot of flexibility. There is nothing there yet, but some version of Jamie’s presentation should appear next week on the GSA working groups archive page here. UPDATE: it is now up


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