The Electronic Design Automation (EDA) industry used to be a bustling bazaar of scrappy startups, along with medium sized companies that dominated a technology space, and big main-line vendors. The annual Design Automation Conference was noisy, hectic, and sprawled over multiple large convention halls. This diversity meant that designers needed to stitch together their chip design flows with point tools from many software tool vendors. As a consequence, design companies all set up dedicated internal methodology teams (or ‘CAD teams’) to evaluate, set up, integrate, and maintain a suite of design software tools for their chip design teams.
That all changed with the strong consolidation that swept through EDA in the early 2000’s. This change mirrored the consolidation experienced across all sectors of the semiconductor industry, including silicon manufacturers, fab equipment vendors, and chip design companies themselves. The EDA industry now counts only 4 major vendors that make up the bulk of the electronic design software market: Synopsys ($3.7B), Cadence Design Systems ($2.7B), Siemens EDA (~$1.8B), and Ansys ($1.7B).
One casualty of this consolidation drive was the abandonment of the open, collaborative business model espoused by the earlier EDA companies. Instead, a closed garden mentality took over that strove to put in place “full flow”, single vendor, exclusive contracts. Despite some limited success, this approach never really succeeded, especially at the major semiconductor houses that provide the bulk of EDA revenues.
There are two major reasons for the failure of this model: Firstly, customers prefer not to tie themselves to a single vendor and lose their leverage in commercial negotiations. But, economics aside, it was always a technical non-starter. The reality is, and always has been, that no single vendor provides competitive technical solutions for the complete range of requirements from major semiconductor customers. This fact has become even more salient with the rapid technical evolution of both Moore’s Law and More-than-Moore that is leading to radical change in design challenges:
- Ultra-low voltage, high speed silicon processes blur the line between analog and digital – high speed interconnect on interposers now routinely requires detailed electromagnetic field analysis. And Dynamic Voltage Drop now contributes about 30% to total path timing at 7nm and below.
- 3D-IC multi-die systems and chiplets have blurred the lines between IC and PCB design techniques.
- Power dissipation has become the number 1 issue for many applications and has blurred the lines between chip and package design. 3D-IC and chiplet designers at the early floorplanning stage now need to worry about thermal management, cooling, heat sinks, and concerns over mechanical stress/warpage reliability.
The result has been a resurgence in the realization that chip design is an incredibly complex multiphysics problem and that no single company has the breadth and depth of technology to solve it all. Ansys, for one, has embraced this reality by leading the industry in reviving the traditional open platform approach to EDA. They have vigorously pursued collaborations, partnerships, and joint developments with other vendors to address deep technical issues facing designers and create unique cross-disciplinary solutions.
The range of Ansys’ collaborations reflects the already broad range of engineering analysis tools it sells. An early step down this road started in 2017 when Ansys and Synopsys partnered to integrate Ansys RedHawk-SC power integrity analysis natively inside Synopsys’ Fusion Compiler implementation product. This collaboration has deepened with the release of Synopsys 3DIC Compiler that relies on Ansys RedHawk-SC Electrothermal for thermal and interposer analysis of 3D-ICs.
Ansys has also collaborated with Siemens EDA to deliver a direct link between Siemens’ Veloce hardware emulator and Ansys PowerArtist RTL power analysis tool. This push towards collaboration was on full display at the recent IDEAS Forum hosted by Ansys where we saw keynote speeches by Tom Lillig, Technology Business Leader at Keysight, Siva Yerramilli, corporate VP for Strategy and System Architects at Synopsys, and Ted Pawela, chief Ecosystem Officer at Altium. There was also a presentation by Gilles Lamant from Cadence Design Systems on joint optical solutions. This is an unprecedented range of competing companies that nevertheless see value in coming together to address specific problems for their customers and I believe it may herald the revival of a more cooperative business trend in building viable electronic design flows.
Ansys has embraced this market development with its own internal reorganization that saw the merger of its Semiconductor division and Electronics division under the leadership of John Lee, GM Electronics and Semiconductor Business Unit. John is a strong proponent of providing open platforms to allow the broadest array of design tools to work together and exchange data. Under his leadership, Ansys has broadened its relationship with Synopsys, shifted its own development priorities to embrace open platforms, and has reached out to complementary tool providers to create industry solutions for Ansys’ diverse customer base. I think this is an interesting trend that may well benefit the EDA industry in general.
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