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Key Takeaways from the TSMC Technology Symposium Part 1

Key Takeaways from the TSMC Technology Symposium Part 1
by Tom Dillinger on 03-20-2016 at 7:00 am

TSMC recently held their annual Technology Symposium in San Jose, a full-day event with a detailed review of their semiconductor process and packaging technology roadmap, and (risk and high-volume manufacturing) production schedules.

This was the 22nd annual symposium, having started in 1995. The prevailing theme of the presentations was: Unleash Your Innovation. As will be discussed, TSMC is significantly expanding the breadth of their technology offering, to “enable customer product innovation” across a wider set of application areas.

As this is the time of the men’s national collegiate basketball tournament, this article will highlight the “Elite Eight” highlights of the symposium. Part 2 will discuss the “Final Four”, and add a few comments about the advanced technology research that TSMC is conducting.

First, a few business highlights from the TSMC presentations:

2015-16 TSMC Business Update

  • 470 customers
  • 1 new customer/week (I found this pretty amazing!)
  • 8900 products shipped, in 220 different technologies
  • 10B chips shipped
  • $2.2B R&D investment planned in 2016
  • acknowledgement to Grand Alliance members, for the benefits of their collaboration with TSMC (i.e., semi equipment suppliers, materials suppliers, EDA tools providers, OIP partners, and customers)

    • a specific focus is being made to be more environmentally green, collaborating with equipment and materials providers on methods to reduce energy demand and reclaim a greater percentage of waste chemicals
  • substantial capacity expansion plans (each phase represents a new building at an existing MegaFab)

    • phase 7 at Fab 12 in Hsinchu completed (to be used for 7nm process development)
    • phases 5 through 7 at Fab 14 completed (for the 16nm production ramp; phases 1 through 4 are for 130um to 40nm production; phases 8 through 11 planned for a 5nm ramp)
    • phases 5 and 6 underway at Fab 15 (preparing for the 10nm ramp, with a 3Q16 target qual date; phases 1 through 4 are for 28nm production)

Now, a (very subjective) ranking of the highlights of the symposium… starting with the “Elite Eight”.

(8) End market diversification is greater than ever, driving TSMC to invest in a greater diversity of process technology offerings.

  • new Ultra Low Power (ULP) offerings: 55ULP/40ULP
  • new 28nm offering — 28HPC+ (relative to 28LP, power/perf of 28HPC is 1.3/0.8, and 28HPC+ is 1.5/0.7)
  • new 16nm offering — 16FFC (FinFET Compact)

The primary focus on driving power dissipation down — lower VDD_min (0.9V for 55/40, 0.7V for 28); lower leakage (updated Vt device targets, new ultra low leakage SRAM bit cells).

Specifically, for the 55/40/28 offerings, TSMC is also investing significantly in embedded flash memory cell development (e.g., eFlash for 40nm in production as of 12/2015; the target for 40ULP is to reduce active power by 30% and standby power by 70%, to be qualified in 2H’2016).

This was the first time I’ve heard of the IoT market as consisting of “low-end”, “middle-end” (55/40ULP, 28HPC+), and “high-end” applications (16FFC). 😉

(7) Specialty technologies will (continue to) lead the semiconductor market growth.

In a relatively flat global semiconductor revenue market for 2015, TSMC reported that their specialty technologies achieved a 21% revenue growth. They provided a similar revenue growth outlook for specialty processes for 2016, indicating that they will be making a 20% wafer capacity investment.

Specialty technologies include:

  • CMOS image sensors: focus on improved pixel size and performance (lower dark current); adding support for near infra-red sensor applications (automotive)
  • MEMS (e.g., improved pressure sensitivity diaphragm-based transducers)
  • chemical sensing (e.g., backside chemical exposure with an electrochemical film layer to create a substrate bias that modulates MOS behavior)
  • biometric sensing (e.g., improved fingerprint sensing through optimal capacitive electrode fabrication on the glass/sensor composite)
  • N40HV process high-voltage applications (e.g., for display drivers)
  • Bipolar-CMOS-DMOS (BCD) processes for power-management IC’s (focus on reducing R_on series resistance/power loss for fast charging applications; also qualification for automotive environments)

(6) TSMC will be groundbreaking on a new, advanced fab in China, with a 16nm production ramp schedules for 2H’2018.

Although this new fab complex was only mentioned briefly, to me, it’s a very significant event.

  • Location: Nanjing City, China, 93 hectares (1.6km x 5.6km)
  • Initial capacity: 20K wafers/mo, 16nm (“Additional phases would be available in the future.”)
  • Schedule: groundbreaking in July, 2016, 2H’2018 mass production

I feel this signifies an unprecedented collaboration between Taiwan and China. And, it is a key piece of the initiative of the Chinese government to develop a more self-sufficient electronics industry, from mobile to high-performance computing applications.

Other companies have fabs in China, to be sure:
https://en.wikipedia.org/wiki/List_of_semiconductor_fabrication_plants

Yet, this is a first for a major foundry source in China with plans to offer a leading process node.

(5) Multiple application-specific design “platforms” will be required.

TSMC has traditionally been very focused on design enablement for customers, from the development (and potentially early, pre-1.0) release of Process Design Kit (PDK) data:

  • models
  • techfiles (physical design, extraction, EM, IR, etc.)
  • design guidelines
  • reference flows (with qualified EDA tools), and
  • foundation-level and interface-standard IP cells


During his presentation at the symposium, Suk Lee, Senior Director, Design Enablement Flows and Services, highlighted that TSMC is undertaking a new initiative — the preparation and qualification of multiple, application-specific platform releases for advanced process nodes.

There will be four platforms released:

  • mobile
  • IoT/wearable
  • automotive
  • high-performance computing

For the new N16FFC process offering, the goal is to support low-power mobile and IoT applications down to a supply voltage of 0.5V.

For automotive applications, such as the Advanced Driver Assist System (ADAS), the platform support must extend to the unique environmental conditions and the stringent reliability requirements. For example, Spice models must be qualified to 150 degrees C. Electromigration rules must also be compliant with these temperatures, and need to be developed in support of a “near-zero PPM” failure rate. All related IP must be re-qualified to these standards.

(One of the symposium Final Four highlights in the next part of this article will discuss how TSMC is specifically addressing the high-performance computing application platform.)

Reference flows are adapted to each platform. Operating at very low VDD necessitates a different approach to timing optimization algorithms in physical design, as new on-chip variation (OCV) stage delay models are required. Indeed, statistical circuit analysis methodologies require a fresh look, as well, due to non-Gaussian probability distributions of key performance parameters.

On top of the application platform requirements, leading technologies are also making more extensive use of lithography multipatterning. Due to asymmetries in the resulting chip structures, designers need to give greater attention to the “coloring” of individual interconnects (and macro/cell pins), to manage performance on critical nets. Electromigration and I*R analysis are significantly impacted by the coloring asymmetries, as well. The suite of physical design, physical verification, and electrical analysis tools need to reflect both advanced litho and unique PVT corner behavior.

Suk Lee hinted at some of the additional multipatterning-related issues for verification and analysis at 7nm, where (scaled) line end-to-line end spacing will be defined by colored “cut masks”.

TSMC is working closely with EDA providers, to ensure the reference flows for each platform utilize the latest techfile and rules data.

At the symposium, TSMC clearly wanted to emphasize the breadth of their technology offering, and their investment in enabling additional application markets — with focus on ultra-low power and automotive requirements, while still maintaining support for high-performance (mobile and compute) centric customers.

The next part of this summary will review the “Final Four” highlights. (I hope your favorite basketball team does well in the tournament. :D)

-chipguy

Also read: Key Takeaways from the TSMC Technology Symposium Part 2


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