The most interesting presentation at the jam-packed TSMC Symposium last week for me was “Advanced Technology Updates” by Dr. BJ Woo. Coincidentally, I met with BJ during my last visit to Fab 12. Much of what we discussed was about TSMC being more aggressive this year but I wasn’t able to really connect the dots until her presentation. The example I will use here is 28nm but it certainly applies to all of the TSMC process nodes moving forward.
First let me tell you that BJ is engaging and a very credible semiconductor executive. She spent the majority of her 30 year career at Intel in Santa Clara designing both DRAM and microprocessors (she has 13 patents). In 2009 BJ joined TSMC taking responsibility for the advanced technology roadmap at 28nm and 20nm and today is Vice President of Business Development.
According to recent press releases and the resulting comments by analysts, who don’t know any better, other foundries are eating away at TSMC’s 28nm stronghold. Articles like that will get you lots of clicks but they are misleading. Remember, there are two versions of 28nm: gate-first and gate-last HKMG. Moving a TSMC gate-last 28nm design that is in production with 90%+ yield to a new gate-first process is absolute madness. Even moving a production design to a new gate-last process that is supposedly “T” compatible (UMC and SMIC) is risky. But of course it will happen because if you are negotiating a better price from one vendor you have to actually be in the position to use another vendor to even be at the negotiation table.
Having the best yielding process does not just give you the lowest cost, it also gives you better design margins and that is the point TSMC made at the symposium. Today TSMC has five versions of 28nm: HP (high performance), HPM (high performance mobile), HPC (high performance computing), HPL (high performance low power), and LP (low power). Two additional processes were added: HPC+ which is an even faster version of HP and ULP which is ultra-low power for IoT and other battery powered applications.
28HPC+ is more compact with 9 and 7 track cell libraries versus 12 and 9 track for 28HPC. The design rules are the same but it has better design margins which offers 15% more performance. 28ULP looks a lot like 55ULP and 40ULP that are already in production. Compared to the associated LP processes, ULP processes can further reduce operating voltages by 20% to 30% to lower both active power and standby power consumption resulting in a 2x-10x increased battery life. IoT and wearable devices are the target applications for ULP processes of course.
The other big 28nm announcement that BJ made is that the TSMC 28nm is now qualified for automotive work which is an industry first. Given the growth of electronics in our cars and the coming autonomous vehicles this is a very big deal for sure.
In the same vein, BJ also talked about a new 16nm process coming called 16FFC, the C meaning compact. It is a more economical version of 16FF+ aimed at cost and power sensitive markets. Power is said to decrease by more than 50% and the pricing will be very competitive for mainstream markets.
Again, when I met with BJ she said TSMC would be very aggressive moving forward and she had a definite twinkle in her eye and now I know why. What a great year for the fabless semiconductor ecosystem, absolutely!
Also read: TSMC Processes GaloreShare this post via:
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