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FinFET Custom Design

FinFET Custom Design
by Paul McLellan on 04-02-2014 at 8:30 pm

At CDNLive, Bob Mullen of TSMC gave a presentation on their new custom FinFET flow, doing design, and verifying designs. At 16nm there are all sorts of relatively new verification problems such as layout dependent effects (LDE) and voltage dependent design rules. We had some of this at 20nm but like most things in semiconductor, it gets harder with each process generation. I’m going to leave verification until another blog.

He wasn’t talking about digital SoC design, which broadly speaking is the same as before. You write RTL, synthesize the design, place and route it and then run verification. Mostly the tools take care of the hard stuff like double patterning. And whoever designed the standard cell libraries took care of all the complicated FinFET stuff. He was talking about custom and analog design where you do actual transistor level layout.

I’m sure you know what a FinFET transistor looks like these days. What you may be less aware of is that they have to be laid out in a sort of matrix. The fin is a fixed size and so the only thing you get to vary about a transistor is how many FinFETs you get to join up in parallel to build a wider transistor. This is often referred to as quantization. In planar devices we used to be able to vary the width and length how we wanted. Actually by the time we got to 20nm this wasn’t really true, the design rules were so restrictive that the transistors were also pretty much laid out in a matrix. To build them, for lithography reasons, the gate material needed to be laid out in parallel lines at the appropriate spacing and then a cut-mask used to split the gate lines up into transistors. So the length of the transistors was pretty much fixed but at least we got to pick the width. With FinFETs we used the same technique but we don’t get to pick the width arbitrarily, just how many fins are controlled by the same signal. So a FinFET design consists of rows of source/drain with rows of gate running orthogonally.

Above is a very simple representation. TSMC doesn’t let anyone see their layout except under NDA so this is actually Cadence’s generic FinFET process used for testing tools early in the whole process. And the planar transistor on the left is nothing like the last planar process at 20nm, it is more like how things looked at 90nm when lithography OPC constraints were a lot more forgiving.

On the right is a FinFET inverter. First thing to note is that the inverter seems to have three gates (red), which is true. Every transistor has to be terminated with dummy gates on either side. You can’t just cut off the diffusion by just ending the polygon like in the planar device on the left. You need to tie it off with a gate. This was actually true at 20nm too, which is one reason I said that the planar transistor was from an old process node. In the middle you can see the red hashed area, that is the cut mask that separates the P and N transistors.

 The first thing TSMC did was build a capability into the PDK to build a “transistor” that took as input how many fins were to be used. It created the layout, including dummy gates and well boundaries.

Then they created a schematic migration methodology to automate much of the migration of designs from 20nm by picking appropriate fin-counts close to simply scaling a planar transistor to 16nm. The voltages are different, the PDKs are different, and the quantized nature of FinFETs needed to be taken into account. But when they were done they would have migrated:

  • Circuit symbols and schematics
  • Hierarchical design configuration view
  • Electrical & Physical design constraints
  • Functional behavioral modeling views
  • Testbench schematics and setups

 However there is still no layout and the schematic is almost certainly going to need to be changed before the cell is finalized. The first step is thus to circuit simulate the schematic using estimated parasitics to get a starting point for getting to a layout.

The next step is rapid analog prototyping, to iterate between layout, extraction, circuit simulation and tweaking transistor sizes and layout constraints. The actual layout is automatically generated under the constraints. Every time the layout changes the parasitics change so hopefully the process converges reasonably fast.

Then onto verification. But that is a topic for another day.

If you have a Cadence account you should be able to find Bob’s CDNLive presentation here.

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