Virtuoso at CDNLive – A Press Briefing With Yuval Shay

Virtuoso at CDNLive – A Press Briefing With Yuval Shay
by Alex Tan on 05-01-2018 at 12:00 pm

Image RemovedAt CDNLive Silicon Valley 2018, I talked with Yuval Shay, Director of Product Management of Cadence Custom IC & PCB Group to scope out some more details on the recent Virtuoso product refresh announced earlier in the morning by Cadence Sr. VP & GM of the same group, Tom Beckley.

Tom shared his view on enabling… Read More


Enabling A Data Driven Economy

Enabling A Data Driven Economy
by Alex Tan on 04-13-2018 at 12:00 pm

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The theme of this year CDNLive Silicon Valley keynote given by Cadence CEO, Lip-Bu Tan evolves around data and how it drives Cadence to make a transition from System Design Enablement (SDE) to Data Driven Enablement (DDE). Before elaborating further, he noted on some CDNLive conference statistics: 120 sessions,… Read More


The CDNLive Keynotes

The CDNLive Keynotes
by Bernard Murphy on 04-25-2017 at 7:00 am

I’m developing a taste for user-group meetings. In my (fairly) recently assumed role as a member of the media, I’m only allowed into the keynotes, but from what I have seen, vendors work hard to make these fresh and compelling each year through big-bang product updates and industry/academic leaders talking about their work in bleeding-edge… Read More


PowerTree — a data repository and simulation platform for PCB power distribution networks

PowerTree — a data repository and simulation platform for PCB power distribution networks
by Tom Dillinger on 02-24-2017 at 12:00 pm

The difficulty of managing the power domains on a complex SoC led to the development of a power format file description, to serve as the repository for data needed for functional and electrical analysis (e.g., CPF, UPF). Yet, what about complex printed circuit boards? How can the power domain information be effectively represented… Read More


Moving up Verification to Scenario Driven Methodology

Moving up Verification to Scenario Driven Methodology
by Pawan Fangaria on 09-11-2015 at 12:00 pm

Verification complexity and volume has always been on the rise, taking significant amount of time, human, and compute resources. There are multiple techniques such as simulation, emulation, FPGA prototyping, formal verification, post-silicon testing, and so on which gain prominence in different situations and at different… Read More


SystemC Co-Simulation of NoCs and IP Blocks

SystemC Co-Simulation of NoCs and IP Blocks
by Paul McLellan on 03-19-2015 at 7:00 am

Verification in general suffers from a couple of fundamental problems. Availability of models and performance of different levels of representation.

The first problem, availability of models, is that you would like to start verification as soon as possible but all the representations are not ready early enough. Obviously … Read More


FinFET Custom Design

FinFET Custom Design
by Paul McLellan on 04-02-2014 at 8:30 pm

At CDNLive, Bob Mullen of TSMC gave a presentation on their new custom FinFET flow, doing design, and verifying designs. At 16nm there are all sorts of relatively new verification problems such as layout dependent effects (LDE) and voltage dependent design rules. We had some of this at 20nm but like most things in semiconductor,… Read More


Automating Analog Verification in Virtuoso

Automating Analog Verification in Virtuoso
by Daniel Payne on 03-31-2014 at 2:00 pm

Digital designers have been automating the functional verification process for many years now, however when you talk to an analog designer about how they do verification you quickly realize that the typical process is quite ad-hoc and little automated. Necessity does create an opportunity so the software engineers at MethodicsRead More


CDNLive World Tour

CDNLive World Tour
by Paul McLellan on 01-28-2014 at 11:00 pm

Image RemovedCDNLive is becoming a real worldwide event, starting in March in San Jose and ending in November in Tel Aviv, Israel.

The complete schedule is:

  • March 11-12th, Santa Clara, California
  • May 19th-21st, Munich, Germany
  • July 15th, Seoul, Korea
  • August 15th, Shanghai, China
  • August 7th, Hsinchu, Taiwan
  • August 11-12th,
Read More

Virtual Platforms, Acceleration, Emulation, FPGA Prototypes, Chips

Virtual Platforms, Acceleration, Emulation, FPGA Prototypes, Chips
by Paul McLellan on 03-12-2013 at 7:13 pm

At CDNLive today Frank Schirrmeister presented a nice overview of Cadence’s verification capabilities. The problem with verification is that you can’t have everything you want. What you really want is very fast runtimes, very accurate fidelity to the hardware and everything available very early in the design … Read More