The difficulty of managing the power domains on a complex SoC led to the development of a power format file description, to serve as the repository for data needed for functional and electrical analysis (e.g., CPF, UPF). Yet, what about complex printed circuit boards? How can the power domain information be effectively represented (for one or more boards), and used as the repository for subsequent analysis? How can electrical analysis be pulled “into the design phase”, reducing the PCB optimization effort? How can the PCB power format information be derived automatically, and submitted for simulation?
Specifically, the issues with accelerating power integrity analysis for a complex power distribution network (PDN) include:
- PDN connectivity is difficult to visualize, as it is embedded in the detailed schematics
- strong version management of the PDN and component model library is required during the design phase, enabling a quick comparison highlighting differences in the PDN design of successive versions
- initial pre-layout simulation support is needed, to help identify any gross errors before layout
- simulation set-up is a pain
Cisco recently shared an example of the magnitude of the power domain topologies from a current product (link below) — e.g., ~20 power rails, ~250 components, and ~500 power nets (including nets around filter components). Specifically, the system-level board design includes a wide diversity of component types, with varied constraints on the allowed I*R (DC) supply voltage drop and component power pin impedance profile versus frequency (AC, with optimized decoupling capacitance sizing and placement).
I recently had the opportunity to chat with Brad Griffin, Product Management Director, Custom IC & PCB Group at Cadence. Brad described how Cadence is helping address the requirement to bring PI analysis forward into the design flow. “With the assistance of customers like Cisco, we have developed an advanced feature in our recent Sigrity Power Integrity and OptimizePI toolset. The PowerTree repository is a unique method to capture and visualize complex board design information and related component model constraints.”
Setup of the PowerTree configuration is straightforward — a screen shot of the “Build Power Tree” dialog is included below.
A screen shot of the PowerTree application representing a complex PDN is included below.
The component bill-of-materials and connectivity netlist is derived from Cadence Allegro. A single view consolidates data across a potentially large number of schematic pages. Component models provide both electrical behavior and verification checking limits. Designers can include additional design constraints and component model data in the PowerTree repository.
Brad highlighted, “From the PowerTree environment, PCB designers can quickly generate and run DC analysis simulations in Sigrity PowerDC, initially from the schematic, and then with detailed layout parasitics. After optimizing the DC profile, the design is then provided to the power integrity expert for decap selection and positioning to optimize the frequency-dependent power impedance profile. The PI expert receives a higher quality design, to start their work with Sigrity OptimizePI. “
Brad and I both acknowledged that power integrity experts are a precious resource, and always overworked. 🙁 The opportunity for board designers to quickly derive and view the power topology and component data using the Sigrity PowerTree feature, then simulate to ensure correct DC margins are provided, will be a tremendous aid to the PI analysis activity.
For more info on the new Sigrity PowerDC and PowerTree features, please follow this link.
For additional insight into the collaboration with Cisco and Cadence on PowerTree, a link to a recent joint presentation at CDNLive is here.
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