For any semiconductor technology node to be adopted in actual semiconductor designs, the very first step is to have a Process Design Kit (PDK) developed for that particular technology node and qualified through several design tools used in the design flow. The development of PDK has not been easy; it’s a tedious, time consuming, and repetitive process to develop and validate various design rules in the silicon during the technology development. Even after readiness of a technology node, PDK development may take several months before any real design can be developed and tested on that technology node. Usually, the process flow is unstable during early phases of technology development and that adds certain amount of inaccuracy in the results, which is later corrected after several iterations.
Now consider today’s advanced process nodes, for example a FinFET 14nm FEOL or a Self-Aligned Quad-Patterned (SAQP) 10nm BEOL. It’s a 3D structure that introduces several complex process rules and constraints in the technology development. The design rules can vary with the contexts of the design constructs. In such a situation, if we keep using the same old method of design rule analysis by using spreadsheet calculations and various process assumptions, it no longer remains predictive and can further delay PDK creation. It’s time for using a predictive Virtual Fabrication Platform to develop and validate design rules for faster and accurate PDK generation. Coventor’sSEMulator3D provides an excellent platform for this new way of PDK generation that can prove extremely productive and worthy for advanced complex technology nodes. It provides accurate models and simulations for predictive analysis of design rules for different design constructs under different contexts.
Consider a self-aligned via V1 placed at the crossing between metals M1 and M2 as shown in figure 1. As is evident from the SEMulator3D predictive structural model and its simulation graphs, the contact area between V1 and M1 is dictated by V1-M2 overlay errors, and not by M2-M1 overlay errors.
Now consider another design situation (as shown in figure 2) where the V1 is between the adjacent corners of M1 and M2. In this case, the contact area between V1 and M1 is dictated by both, V1-M2 overlay errors and M2-M1 overlay errors. Under the even tighter overlay controls, the contact area is significantly reduced compared to the crossing case in figure1. The reduction in the contact area has to be limited in order to preserve the yield and reliability criteria, otherwise such construct is disqualified. Improvements in design finishing, OPC, process or design rules can all be driven from such an analysis.
The SEMulator3D Virtual Fabrication Platform can develop such design-sensitive rule analysis in a physically predictive sense to help produce more robust high quality design rule checking.
The SEMulator3D’s predictive modeling along with Virtual Metrology and Expeditor can also provide accurate process variations that can be used to gain better yield and equip designers to accurately predict electrical behavior.
Parasitic extraction is another key task in PDK development. SEMulator3D has the capability to produce meshes for finite element analysis based on its process-predictive physical models. The parasitic values extracted from SEMulator3D models are significantly more accurate than those from typically used geometry-based models.
The above capabilities in SEMulator3D make it an ideal and powerful platform for generation of PDKs for complex technology nodes. It saves several months of time in producing PDKs for new technologies and at the same time provides robust and accurate design rules, thus providing huge benefits to early adopters as well as foundries and IDMs.
The success of SEMulator3D has led Coventor to expand in Taiwan, a region buzzing with semiconductor technology development and chip manufacturing. Last week Coventor made a press release about opening its office near Hsinchu Science Park in Taiwan. The idea is to better serve Coventor’s large customer base in that region and also expand the use of SEMulator3D Virtual Fabrication Platform among other foundries, IDMs and memory manufacturers.
Advanced 3D memory technologies for DRAM and NAND Flash as well as 3D FEOL logic processes for FinFETs represent significant development challenges for foundries and fables teams. The SEMulator3D Virtual Fabrication Platform enables design and process architects to effectively collaborate at the physical process level and integrate new technologies into the manufacturing process. Thus SEMulator3D also provides an excellent platform for new technology development. It significantly reduces silicon learning cycles and capital expenditure in new technology development.
Pawan Kumar Fangaria
Founder & President at www.fangarias.com