WP_Term Object
(
    [term_id] => 82
    [name] => Coventor
    [slug] => coventor
    [term_group] => 0
    [term_taxonomy_id] => 82
    [taxonomy] => category
    [description] => 
    [parent] => 14433
    [count] => 42
    [filter] => raw
    [cat_ID] => 82
    [category_count] => 42
    [category_description] => 
    [cat_name] => Coventor
    [category_nicename] => coventor
    [category_parent] => 14433
)

Intel has Another First for 14nm Production!

Intel has Another First for 14nm Production!
by Daniel Nenni on 12-10-2014 at 7:00 am

An interesting thing happened while I was researching a slide from Bill Holt’s “Advancing Moore’s Law” presentation at last month’s analyst meeting. Slide #19 mentioned that Intel was the first to use “air gap” dielectric spaces to improve performance in a digital logic flow for microprocessors. I know a certain foundry that is actively researching air gapping but for production this is a pretty major announcement that did not get the proper accolades in my opinion. The benefit of using the “ultimate” low-K dielectric can be huge however the devil is in the details.

To clarify I’m hoping the esteemed members of SemiWiki can help with the following questions:

[LIST=1]

  • What (additional) design restrictions does this impose?
  • What are the metal width and space options, to enable the “sealing” dielectric to surround the air gap?
  • What happens around vias?
  • What % of a typical wire could have a surrounding air gap?
  • Are general SoC designers ready for the additional tradeoffs (less wiring flexibility for reduced RC interconnect delays and noise coupling)?

    The first mention of this I found was from a paper at the 2010 International Interconnect Technology Conference. Researchers from Intel confirmed that the design constraint of a fixed spacing between interconnect lines allows for the use of air gaps in manufacturing to increase circuit speeds. Coincidentally one of the other references that came up when Googling around is a blog on the Coventor website “Got Air Gaps?” from Ryan Patz of Applied Materials which is definitely worth a read. “Coincidentally” because I will be moderating a panel with Coventor at IEDM next week in San Francisco on process variation:

    Survivor: Variation in the 3D Era
    It’s a jungle out there. The era of 3D semiconductors, 3D NAND Flash, FinFETS and unprecedented process complexity introduces new pitfalls for the cunning engineer to overcome. Find out how the best and the brightest are outwitting the competition with creative ways to navigate the treacherous landscape of advanced IC design and manufacturing. They know the key to survival in dealing with process variation is to …

    Reduce It. Contain It. Understand it.
    Join a group of rugged survivors at an interactive panel discussion, moderated by one of the original castaways from the IC island, Daniel Nenni of SemiWiki, and featuring:

    • Rich Wise, Lam Research
    • Jeffery Smith, TEL America
    • Tomasz Brozek, PDF Solutions
    • Tom Dillinger, Oracle Corporation
    • Jan Hoentschel, GlobalFoundries
    • David Fried, Coventor

    Location: “Carmel Room” at Hotel Nikko, San Francisco
    Date: Tuesday, December 16, 2014
    Time: 5:30pm -8:30pm (Cocktails and hors d’oeuvres) Panel begins at 6:00pm

    MORE INFO HERE

    You do not need an IEDM badge for this so please stop by if you can and meet the people behind the semiconductors that make modern life, well, modern.

    About Coventor

    Coventor, Inc. is the market leader in automated design solutions for developing semiconductor process technology, as well as micro-electromechanical systems (MEMS). Coventor serves a worldwide customer base of integrated device manufacturers, memory suppliers, fabless design houses, independent foundries, and R&D organizations. Its SEMulator3D modeling and analysis platform is used for fast and accurate ‘virtual fabrication’ of advanced manufacturing processes, allowing engineers to understand manufacturing effects early in the development process and reduce time-consuming and costly silicon learning cycles. Its MEMS design solutions are used to develop MEMS-based products for automotive, aerospace, industrial, defense, and consumer electronics applications, including smart phones, tablets, and gaming systems. The company is headquartered in Cary, North Carolina and has offices in California’s Silicon Valley, Waltham, Massachusetts, and Paris, France. More information is available at http://www.coventor.com.


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