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IMEC Technology Forum at SEMICON – Coventor could save you billions!

IMEC Technology Forum at SEMICON – Coventor could save you billions!
by Scotten Jones on 07-22-2016 at 7:00 am

 The development of leading edge semiconductor technology is incredibly expensive, with estimates ranging from a few to several billion dollars for new nodes. The time to develop a leading edge process is also a critical competitive issue with some of the largest opportunities awarded based on who is first to yield on a new node.

Being late to market can cost a semiconductor company billions of dollars in lost opportunities! Coventor produces SEMulator3D, a modeling platform that enables development engineers to simulate process flows in full 3D to test and refine them before running wafers, reducing development costs and speeding up time to market. David Fried is the CTO of Coventor and he presented at the IMEC Technology Forum (ITF) on Monday before SEMICON. I was at David’s presentation and I also had the opportunity to interview him on Wednesday during the show.

Coventor SEMICON Presentation Slides

Coventor was formed in 1996 making it approximately 20 years old. The original focus of Coventor was on MEMS simulation and EDA and that led to the development of a core competency in 3D modeling (MEMS devices typically have a 3D structures). Around 2004/2005 Intel was a Coventor investor and suggested migrating to semiconductor simulation and SEMulator3D was born.

David Fried’s path to working at Coventor is an interesting one in that he was a user of the product before becoming CTO of Coventor. David was working at IBM and had just finished 65nm development. David was tasked with 22nm development and he recognized the need for a new development paradigm. David brought in Coventor to IBM; he helped Coventor understand what IBM needed and Coventor was very responsive to the needs. After he finished up his work on IBM’s 22nm SOI development, David joined Coventor as the CTO. Coventor has rolled out the SEMulator3D platform to semiconductor companies and they are now also seeing adoption at equipment and materials companies.

The SEMulator3D platform is focused on process prediction and structural integrity. You feed a layout into the model using standard formats such as GDSII and define your process steps and the platform produces a full step by step 3D model. You can step through the resulting model and rotate and zoom in on the resulting structure. More importantly, you can measure and perform 3D checking on the resulting models, allowing quantitative analysis of the impact of process changes or variations. The process flow is built up using functional models, for example to define an etch process you put in etch rate, selectivity, time and lateral bias, you can also input optional parameters such as pattern dependence, sputtering component, etc. The interface is windows based and easy to use with dropdown menus. Typically, the platform is deployed across an entire development group. The platform has been used for process development, process documentation, metrology development and many other applications.

David’s presentation was titled “Technology Development: The “In Between”.

In David’s presentation he showed the historical technology development method:

  • Test chip design – characterization structures for known/expected targets and challenges.
  • Run experimental lots – do splits, short loops, Front End Of Line (FEOL), Back End Of Line (BEOL) or full flows.
  • Characterization – use inline metrology, offline physical testing and electrical testing.
  • Feedback – run engineering analysis and change the process of record. You then go back to step 2. You repeat this loop every one to three months.
  • New Test Chip – as you learn you may need to go back and redesign the test chip based on what you have learned (go back to step 1). This typically takes place approximately once a year.

    In my interview with David he noted that a development cycle from steps 1. to 4. listed above typically takes three months and costs $50 million dollars!

    Due to growing process complexity, the need to account for atomic scale variation and the combination of new elements, development continues to get more complex. ASML has noted that multi-patterning for the 7nm/5nm increases lithography masks and steps by 5x and deposition, clean and etch steps by 5x, and that is not even counting additional inspection and metrology. Clearly some way to simplify, reduce cost and accelerate process development is needed.

    SEMulator3D addresses this problem by enabling virtual fabrication for:

    • Evaluation of research concepts – make the big branch decision about what technology directions to pursue.
    • Vetting of variations – look for problems lurking in your planned process flow.
    • Combine research elements – when you run into problems you can combine and reevaluate technological options.

    As you develop a technology there is a series of decisions:

    • Big branch – for example FDSOI versus FinFET.
    • Then as you move out the branches do you want to do gate first or gate last.
    • Then you move on to, merged S/D or isolated S/D or NMOS or PMOS metallization first.

    As you move onto a branch and further out the branch, starting over is more and more expensive. With virtual fabrication you map out the braches before being forced to make decisions.

    David went on to show examples of the use of virtual fabrication:

    • IMEC and Applied Materials for 7nm lower gate resistivity.
    • IBM 22nm SOI yield optimization.
    • Global Foundries 14nm FinFET specification setting and variation reduction.
    • IMEC 5nm process capability evaluation.
    • TEL evaluating equipment requirements and patterning options for 10nm.

    In our interview he also mentioned work to be published where over a million virtual wafers were run through SEMulator3D for 5nm process evaluation.

    The use of virtual fabrication in the SEMulator3D platform can eliminate entire development cycles reducing cost and speeding up development. It is also possible to do things like the million wafer virtual run to evaluate variation that are simply not possible to do by actually running wafers. Virtual fabrications runs take minutes to complete as opposed to months for test runs.

    In summary virtual fabrications can:

    • Map the big branch decisions prior to running wafers.
    • Avoid alligators in the water due to process variation.
    • Direct trips back to the well earlier in the development schedule.

    The bottom line is the development of processes can be less expensive, faster and the resulting process can be more highly optimized. Engineers all across the industry have recognized the need for this new virtual fabrication paradigm. In today’s market place, winning the development competition can bring in billions of dollars in business opportunities that might otherwise go to a competitor. The massive financial impact of virtual fabrication is now being felt in the boardroom!

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