Vertical NAND Flash

You may know that up until now NAND flash has been a planar technology. But just as with SoC processes where we have had to go vertical to FinFETs, NAND flash has reached the limitations of scaling in the 20nm nodes and is also going vertical. It is not just a lithography issue but there are also reliability and voltage scaling issues. The solution is to stack memory cells vertically, increasing cell density without needing additional area for the memory array. These approaches are called either 3D NAND flash or Vertical NAND flash.

Coventor have put together a solution based on Terabit Cell Array Transistor (TCAT) technology, using SEMulator3D to evaluate process variations in the NAND string formation, especially during channel etching and contact formation. This SEMulator model has been reverse engineered from publicly available information such as conference papers and published SEM images. SEMulator3D is a predictive 3D modeling platform ideal for this sort of analysis due to its predictive modeling performance and accuracy.

Each memory cell is a gate-all-around device consisting of a metal gate atop a charge-trap flash stack, surrounding the string’s polysilicon channel; a gate-last flow is used for integrating the metal gate. The gates of neighboring NAND strings are tied together to form horizontally-oriented wordlines, which can be accessed at the edge of the flash device through contacts arranged in a staircase-like structure. See the diagram above.

I talked to Sandy Wen of Coventor about the new white paper that she has written on this work. Before joining Coventor, her background was in process equipment, in particular etch, where she worked for Applied Materials and for LAM Research. She is about to start a new project since her maternity leave starts imminently.

So how do you build such a complex 3D structure? The details are all in the white paper but the 50,000′ view is in the pictures below.

Using the model it is possible to investigate stability, sensitivity, and yield issues. For example, a parallel DOE of 180 runs was executed using SEMulator3D’s Expeditor batch processing capability. Etch process parameters such as nitride taper, lateral etch bias and oxide-to-nitride selectivity were varied, and the resulting channel cross-sectional areas were measured.The resulting virtual metrology data demonstrated the narrow process window for this cyclic etch. To ensure the channel etch reaches the bottom contact, the sidewall angle for each nitride layer must be maintained at 89° or 90°, while the polymer removal must be kept high enough to enable the etch to reach the bottom. When the sidewall angle for the nitride is 88°, the channel etch does not reach the contact bottom, and it has zero channel-to-ground contact area. In contrast, increasing the lateral etch bias in the polymer removal cycle can ensure that the etch reaches the channel bottom, but it comes at the expense of dimensional expansion at the top of the plug, another unacceptable feature.

If this was a real process being designed, rather than a model that has been reverse engineered, this sort of analysis using virtual metrology would save a huge amount of wafer-processing resources and, since it doesn’t require a full cycle through the fab, is also much quicker in getting defining the boundaries for the various parameters for train-and-error processing using real silicon. This is just one of the areas investigated in the white paper.

The bottom line is that, as with all advanced processing such as FinFETs, the interactions between different modules and understanding defect evolution has become increasingly difficult. Virtual fabrication techniques allow issues to be anticipated early, reducing development time and saving silicon runs.

The white paper can be found here.