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Mapping Focus and Dose onto BEOL Fabrication Effects

Mapping Focus and Dose onto BEOL Fabrication Effects
by Tom Simon on 03-16-2015 at 7:00 pm

With today’s ArF based lithography using 193nm wavelength light, we are hard up against the limitations imposed by the Raleigh equation. Numerous clever things have been devised to maximize yield and reduce feature size. These include 2 beam lithography, multiple patterning, immersion litho processes to improve NA, thinner resists, etc. While we wait for EUV to become feasible, those responsible for manufacturing current production chips work with tuning the dozens of aspects in the existing lithography and fabrication process.

We have talked before about the utility of modeling what happens during the IC fabrication process. The ability to simulate the outcomes of fabrication steps is enormously valuable. Coventor’s Semulator3D is a proven tool for performing these simulations. They have a number of white papers on their website that go through the process step by step. The BEOL paper that they feature on this page highlights a tri-layer mask process that uses a thin photo-resist to improve transfer of the aerial image. The latent image is also improved by the middle anti-reflective layer which avoids reflected interference patterns in the resist. These can notably affect edge definition and can undercut the resist at the bottom.

The Coventor Semulator3D shows exactly what happens during processing. This is invaluable in determining the reliability and electrical properties of the resulting wafer. However the developed resist image depends on a myriad of factors. So before we can look at the effects of wafer processing, we need to have a good starting point with physically accurate resist geometry. Focus and dose both have profound effect on the resist sensitization. This is often visualized with a Bossung curve such as that show here from Chris Mack’s excellent lithography lecture series.

Let’s say we wanted to model the whole process from litho to fabrication. This is exactly what Coventor, Panoramic Technology and ASMLdid in material they showed at SPIEa few weeks ago. They used HyperLith from Panoramic Technology to predict the resist contours at a variety of doses and defocus values (0 to +/-50nm). We can see the wide variation in resist quality. Then they took this output and ran it through Coventor’s Semulator3D to see what the resultant wafers would look like.

Coventor can run simulations using their SWA (side wall angle) Variation and look at results with a range of side wall angles. The tradeoff here is line width versus line spacing. If the line widths are too small you have opens in the interconnect and high resistance that can affect circuit operation. If the line to line spacing becomes too small it’s possible to get shorts or proximity failures.

The flow that was used in their SPIE material shows a matrix of dose and defocus values that is then run through Semulator3D with SWA variation. This provides a comprehensive set of data to help understand yield effects. I was lucky to speak with Bill Clark who works in Semiconductor Process and Integration Engineering at Coventor after the SPIE conference. He explained in more detail how this data was prepared. The resist masks came over from Panoramic’s Hyperlith as STL files. Then in Semulator3D they used the Expiditer option to perform batch runs on the dose and focus values with SWA Variation. The output is available in CSV for further processing as needed. Or as you can see the results are available to examine visually.

According to Bill, this demonstration shows a unique approach to better analyzing effects that occur during lithography and fabrication. Hopefully using analytical software in this fashion will help improve visibility into the manufacturing process with the goal of improving yield.

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