Fully Self-Aligned 6-Track and 7-Track Cell Process Integration

Fully Self-Aligned 6-Track and 7-Track Cell Process Integration
by Fred Chen on 08-23-2020 at 6:00 am

Fully Self Aligned 6 Track and 7 Track Cell Process Integration

For the 10nm – 5nm nodes, the leading-edge foundries are designing cells which utilize 6 or 7 metal tracks, entailing a wide metal line for every 4 or 5 minimum width lines, respectively (Figure 1).

Figure 1. Left: a 7-track cell. Right: a 6-track cell.

This is a fundamental vulnerability for lithography, as defocus can change… Read More


EUV faces Scylla and Charybdis

EUV faces Scylla and Charybdis
by Fred Chen on 08-03-2020 at 6:00 am

EUV faces Scylla and Charybdis

It is now time for the EUV community to realize they are caught between the proverbial Scylla and Charybdis. In Greek mythology, the two monsters terrorized ships that were unlucky enough to pass between them. By avoiding one, you approached the other.

S for Scylla, or Stochastics

Scylla was a former beautiful nymph turned into

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Application-Specific Lithography: a 28 nm Pitch DRAM Active Area

Application-Specific Lithography: a 28 nm Pitch DRAM Active Area
by Fred Chen on 07-19-2020 at 2:00 pm

Application Specific Lithography 28 nm Pitch DRAM Active Area

In the recent DRAM jargon, “1X”, “1Y”, “1Z”, etc. have been used to express all the sub-20 nm process generations. It is almost possible now to match them to real numbers which are roughly the half-pitch of the DRAM active area, such as 1X=18, 1Y ~ 17, etc. At this rate, 14 nm is somewhere around

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Application-Specific Lithography: The 5nm 6-Track Cell

Application-Specific Lithography: The 5nm 6-Track Cell
by Fred Chen on 07-05-2020 at 10:00 am

Application Specific Lithography The 5nm 6 Track Cell

The 5nm foundry (e.g., TSMC) node may see the introduction of 6-track cells (two double-width rails plus four minimum-width dense lines) with a minimum metal pitch in the neighborhood of 30 nm. IMEC had studied a representative case as its ‘7nm’ case [1]. TSMC had some published 5nm test structures which looked like… Read More


The Stochastic Impact of Defocus in EUV Lithography

The Stochastic Impact of Defocus in EUV Lithography
by Fred Chen on 06-28-2020 at 6:00 am

The Stochastic Impact of Defocus in EUV Lithography

The stochastic nature of imaging has received a great deal of attention in the area of EUV lithography. The density of EUV photons reaching the wafer is low enough [1] that the natural variation in the number of photons arriving at a given location can give rise to a relatively large standard deviation.

In recent studies [2,3], it … Read More


Feature-Selective Etching in SAQP for Sub-20 nm Patterning

Feature-Selective Etching in SAQP for Sub-20 nm Patterning
by Fred Chen on 06-02-2020 at 10:00 am

Feature Selective Etching in SAQP for Sub 20 nm Patterning

Self-aligned quadruple patterning (SAQP) is the most widely available technology used for patterning feature pitches less than 38 nm, with a projected capability to reach 19 nm pitch. It is actually an integration of multiple process steps, already being used to pattern the fins of FinFETs [1] and 1X DRAM [2]. These steps, shown… Read More


Contact Resistance: The Silent Device Scaling Barrier

Contact Resistance: The Silent Device Scaling Barrier
by Fred Chen on 05-24-2020 at 6:00 am

Contact Resistance The Silent Device Scaling Barrier

Moore’s Law has been about device density, specifically transistor density, increasing every certain number of years. Although cost is the most easily grasped advantage, there are two other benefits: higher performance (speed) and reduced power. When these benefits are compromised, they can also pose a scaling limitation.

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Lithography Resolution Limits: Line End Gaps

Lithography Resolution Limits: Line End Gaps
by Fred Chen on 05-01-2020 at 6:00 am

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In a previous article [1], the Rayleigh criterion was mentioned as the resolution limit for the distance between two features. On the other hand, in a following article [2], the minimum pitch was mentioned for the resolution limit for arrayed features. In this article, we reconcile the two by considering gaps between arrayed features,… Read More


Lithography Resolution Limits – Arrayed Features

Lithography Resolution Limits – Arrayed Features
by Fred Chen on 04-17-2020 at 6:00 am

Lithography Resolution Limits Arrayed Features

State-of-the-art chips will always include some portions which are memory arrays, which also happen to be the densest portions of the chip. Arrayed features are the main targets for lithography evaluation, as the feature pitch is well-defined, and is directly linked to the cost scaling (more features per wafer) from generation… Read More


Lithography Resolution Limits: Paired Features

Lithography Resolution Limits: Paired Features
by Fred Chen on 04-07-2020 at 10:00 am

Lithography Resolution Limits Paired Features

As any semiconductor process advances to the next generation or “node”, a sticky point is how to achieve the required higher resolution. As noted in another article [1], multipatterning (the required use of repeated patterning steps for a particular feature) has been practiced already for many years, and many have… Read More