Application-Specific Lithography: 5nm Node Gate Patterning

Application-Specific Lithography: 5nm Node Gate Patterning
by Fred Chen on 09-08-2022 at 6:00 am

Blur Limitations for EUV Exposure

It has recently been revealed that the N5 node from TSMC has a minimum gate pitch of 51 nm [1,2] with a channel length as small as 6 nm [2]. Such a tight channel length entails tight CD control in the patterning process, well under 0.5 nm. What are the possible lithography scenarios?

Blur Limitations for EUV Exposure

A state-of-the-art

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Spot Pairs for Measurement of Secondary Electron Blur in EUV and E-beam Resists

Spot Pairs for Measurement of Secondary Electron Blur in EUV and E-beam Resists
by Fred Chen on 08-14-2022 at 8:00 am

Spot Pairs for Measurement of Secondary Electron Blur in EUV

There is growing awareness that EUV lithography is actually an imaging technique that heavily depends on the distribution of secondary electrons in the resist layer [1-5]. The stochastic aspects should be traced not only to the discrete number of photons absorbed but also the electrons that are subsequently released. The electron… Read More


The Electron Spread Function in EUV Lithography

The Electron Spread Function in EUV Lithography
by Fred Chen on 06-07-2022 at 6:00 am

Electron Spread EUV

To the general public, EUV lithography’s resolution can be traced back to its short wavelengths (13.2-13.8 nm), but the true printed resolution has always been affected by the stochastic behavior of the electrons released by EUV absorption [1-5].

A 0.33 NA EUV system is expected to have a diffraction-limited point spread… Read More


EUV Resist Absorption Impact on Stochastic Defects

EUV Resist Absorption Impact on Stochastic Defects
by Fred Chen on 04-03-2022 at 10:00 am

EUV Resist Absorption Impact on Stochastic Defects 1

Stochastic defects continue to draw attention in the area of EUV lithography. It is now widely recognized that stochastic issues not only come from photon shot noise due to low (absorbed) EUV photon density, but also the resist material and process factors [1-4].

It stands to reason that resist absorption of EUV light, which is … Read More


Etch Pitch Doubling Requirement for Cut-Friendly Track Metal Layouts: Escaping Lithography Wavelength Dependence

Etch Pitch Doubling Requirement for Cut-Friendly Track Metal Layouts: Escaping Lithography Wavelength Dependence
by Fred Chen on 03-27-2022 at 6:00 am

Etch Pitch Doubling Requirement

The 5nm foundry node saw the arrival of 6-track standard cells with four narrow routing tracks between wide power/ground rails (Figure 1a), with minimum pitches of around 30 nm [1]. The routing tracks require cuts [2] with widths comparable to the minimum half-pitch, to enable the via connections to the next metal layer with the… Read More


Horizontal, Vertical, and Slanted Line Shadowing Across Slit in Low-NA and High-NA EUV Lithography Systems

Horizontal, Vertical, and Slanted Line Shadowing Across Slit in Low-NA and High-NA EUV Lithography Systems
by Fred Chen on 01-11-2022 at 6:00 am

EUV shadowing across slit

EUV lithography systems continue to be the source of much hope for continuing the pace of increasing device density on wafers per Moore’s Law. Recently, although EUV systems were originally supposed to help the industry avoid much multipatterning, it has not turned out to be the case [1,2]. The main surprise has been the

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Contrast Reduction vs. Photon Noise in EUV Lithography

Contrast Reduction vs. Photon Noise in EUV Lithography
by Fred Chen on 05-30-2021 at 6:00 am

Contrast Reduction vs. Photon Noise in EUV Lithography

The stochastic behavior of images formed in EUV lithography has already been highlighted by a number of authors [1-3]. How serious it appears depends on the pixel size with which the photons are bunched. Generally, though, for features of around 20 nm or less, even 1 nm can have at least a +/- 15% gradient across it, which is still a

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SALELE Double Patterning for 7nm and 5nm Nodes

SALELE Double Patterning for 7nm and 5nm Nodes
by Fred Chen on 03-28-2021 at 6:00 am

SALELE Double Patterning for 7nm and 5nm Nodes 4

In this article, we will explore the use of self-aligned litho-etch-litho-etch (SALELE) double patterning for BEOL metal layers in the 7nm node (40 nm minimum metal pitch [1]) with DUV, and 5nm node (28 nm minimum metal pitch [2]) with EUV. First, we mention the evidence that this technique is being used; Xilinx [3] disclosed the… Read More


Calculating the Maximum Density and Equivalent 2D Design Rule of 3D NAND Flash

Calculating the Maximum Density and Equivalent 2D Design Rule of 3D NAND Flash
by Fred Chen on 02-21-2021 at 10:00 am

3D NAND Flash unit cell

I recently posted an insightful article [1] published in 2013 on the cost of 3D NAND Flash by Dr. Andrew Walker, which has since received over 10,000 views on LinkedIn. The highlight was the plot of cost vs. the number of layers showing a minimum cost for some layer number, dependent on the etch sidewall angle. In this article, the same… Read More


Fully Self-Aligned 6-Track and 7-Track Cell Process Integration

Fully Self-Aligned 6-Track and 7-Track Cell Process Integration
by Fred Chen on 08-23-2020 at 6:00 am

Fully Self Aligned 6 Track and 7 Track Cell Process Integration

For the 10nm – 5nm nodes, the leading-edge foundries are designing cells which utilize 6 or 7 metal tracks, entailing a wide metal line for every 4 or 5 minimum width lines, respectively (Figure 1).

Figure 1. Left: a 7-track cell. Right: a 6-track cell.

This is a fundamental vulnerability for lithography, as defocus can change… Read More