NILS Enhancement with Higher Transmission Phase-Shift Masks

NILS Enhancement with Higher Transmission Phase-Shift Masks
by Fred Chen on 07-24-2023 at 8:00 am

Figure 1. NILS is improved

In the assessment of wafer lithography processes, normalized image log-slope (NILS) gives the % change in width for a given % change in dose [1,2]. A nominal NILS value of 2 indicates 10% change in linewidth for 10% change in dose; the % change in linewidth is inversely proportional to the NILS. In a previous article [2], it was shown… Read More


Assessing EUV Wafer Output: 2019-2022

Assessing EUV Wafer Output: 2019-2022
by Fred Chen on 06-26-2023 at 6:00 am

Assessing EUV Wafer Output 2019 2022

At the 2023 SPIE Advanced Lithography and Patterning conference, ASML presented an update on its EUV lithography systems in the field [1]. The EUV wafer exposure output was presented and is shown below in table form:

From this information, we can attempt to extract and assess the EUV wafer output per quarter. First, since there … Read More


Application-Specific Lithography: 28 nm Pitch Two-Dimensional Routing

Application-Specific Lithography: 28 nm Pitch Two-Dimensional Routing
by Fred Chen on 06-19-2023 at 6:00 am

Brightfield (red) and darkfield (purple) sidelobes in 84 nm

Current 1a-DRAM and 5/4nm foundry nodes have minimum pitches in the 28 nm pitch range. The actual 28 nm pitch patterns are one-dimensional active area fins (for both DRAM and foundry) as well as one-dimensional lower metal lines (in the case of foundry). One can imagine that, for a two-dimensional routing pattern, both horizontal… Read More


Curvilinear Mask Patterning for Maximizing Lithography Capability

Curvilinear Mask Patterning for Maximizing Lithography Capability
by Fred Chen on 05-09-2023 at 10:00 am

Curvilinear 1

Masks have always been an essential part of the lithography process in the semiconductor industry. With the smallest printed features already being subwavelength for both DUV and EUV cases at the bleeding edge, mask patterns play a more crucial role than ever. Moreover, in the case of EUV lithography, throughput is a concern, … Read More


Resolution vs. Die Size Tradeoff Due to EUV Pupil Rotation

Resolution vs. Die Size Tradeoff Due to EUV Pupil Rotation
by Fred Chen on 03-02-2023 at 10:00 am

Resolution vs. Die Size Tradeoff Due to EUV Pupil Rotation

The many idiosyncrasies of EUV lithography affect the resolution that can actually be realized. One which still does not get as much attention as it should is the cross-slit pupil rotation [1-3]. This is a fundamental consequence of using rotational symmetry in ring-field optical systems to control aberrations in reflective… Read More


KLAC- Weak Guide-2023 will “drift down”-Not just memory weak, China & logic too

KLAC- Weak Guide-2023 will “drift down”-Not just memory weak, China & logic too
by Robert Maire on 02-06-2023 at 6:00 am

KLAC Tencor SemiWiki

-Business will “drift down” over the course of 2023
-Not just memory is weak- China issue, foundry/logic slowing
-March guide worse than expected (Like Lam)
-Backlog likely saw push outs & cancelations but still long

Good quarter but weak guide

Much as we saw with Lam, KLA reported a beat on the December quarter… Read More


ASML – Powering through weakness – Almost untouchable – Lead times exceed downturn

ASML – Powering through weakness – Almost untouchable – Lead times exceed downturn
by Robert Maire on 01-26-2023 at 10:00 am

Robert Maire Bloomberg

-Demand far exceeds supply & much longer than any downturn
-Full speed ahead-$40B in solid backlog provides great comfort
-ASP increase shows strength- China is non issue
-In a completely different league than other equipment makers

Reports a good beat & Guide

Revenues were Euro6.4B with system sales making up Euro4.7B… Read More


SPIE Advanced Lithography + Patterning

SPIE Advanced Lithography + Patterning
by Admin on 01-25-2023 at 2:43 pm

The event for emerging technology in the semiconductor industry

Attend and hear research, challenges, and breakthroughs as you gather with colleagues in San Jose

Join other leading researchers who are solving challenges in optical and EUV lithography, patterning technologies, metrology, and process integration for semiconductor… Read More


Secondary Electron Blur Randomness as the Origin of EUV Stochastic Defects

Secondary Electron Blur Randomness as the Origin of EUV Stochastic Defects
by Fred Chen on 01-09-2023 at 10:00 am

Secondary Electron Blur Randomness as the Origin of EUV Stochastic Defects

Stochastic defects in EUV lithography have been studied over the last few years. For years, the Poisson noise from the low photon density of EUV had been suspected [1,2]. EUV distinguishes itself from DUV lithography with secondary electrons functioning as intermediary agents in generating reactions in the resist. Therefore,… Read More


Application-Specific Lithography: 5nm Node Gate Patterning

Application-Specific Lithography: 5nm Node Gate Patterning
by Fred Chen on 09-08-2022 at 6:00 am

Blur Limitations for EUV Exposure

It has recently been revealed that the N5 node from TSMC has a minimum gate pitch of 51 nm [1,2] with a channel length as small as 6 nm [2]. Such a tight channel length entails tight CD control in the patterning process, well under 0.5 nm. What are the possible lithography scenarios?

Blur Limitations for EUV Exposure

A state-of-the-art

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