WP_Term Object
(
    [term_id] => 82
    [name] => Coventor
    [slug] => coventor
    [term_group] => 0
    [term_taxonomy_id] => 82
    [taxonomy] => category
    [description] => 
    [parent] => 14433
    [count] => 42
    [filter] => raw
    [cat_ID] => 82
    [category_count] => 42
    [category_description] => 
    [cat_name] => Coventor
    [category_nicename] => coventor
    [category_parent] => 14433
    [is_post] => 1
)

SEMulator3D on Silicon Cloud International

SEMulator3D on Silicon Cloud International
by Paul McLellan on 06-22-2015 at 7:00 am

 Almost exactly a year ago I wrote about Silicon Cloud International (SCI). Their mission is to help smaller countries that have targeted semiconductor design as a way to move up the technology ladder from low-cost manufacturing. Last year everything was in the future but SCI now have their first two centers up and running. The first, a pilot program, was announced at the end of last year and is in UAE. The second, announced a couple of months ago is in Singapore (which is also SCI’s home).

See also National Semiconductor Education in the Cloud

 In EDA the pioneer in using the cloud was probably Nimbic (now part of Mentor). If the cloud is going to work anywhere in EDA then these types of applications that require hugely scalable compute resources, don’t involve gigabyte files, and don’t contain the entire company crown jewels are likely to be the first places. I just wrote a blog last week on the IBM announcement of its library characterization tools in the cloud, with some skepticism about doing an entire design in the cloud.

See also IBM Design Tools in the Cloud: Big News or Old News?

Another area that seems a good match is virtual fabrication whereby a full 3D model of a part of a process is built up from the process recipe and a small amount of layout. This can then be verified. The process is computationally expensive and a lot of verification can be run in parallel, so the scalable nature of the cloud is idea.

At DAC on the SCI booth I watched a demo of Coventor’s SEMulator3D Virtual Fabrication platform with broad parallel computing offered by Silicon Cloud. Coventor is calling this 3D Design-Technology Checking (3D-DTC).

SEMulator3D enables process predictive virtual fabrication of any design in any process flow. I’ve blogged about this before, most recently about vertical flash memory. Using SEMulator3D’s Automation features, users can easily virtual fabricate hundreds or thousands of models representing process or design variations, and then check them in true 3D space for critical yield criteria. The broad computational resource added by Silicon Cloud allows this to be done across a huge process space in a very short time. This especially important for companies that do not have extensive compute farms available (or “private cloud” seems to be the trendy word for a compute farm these days).

See also Vertical NAND Flash


So what was the demo? Just a single design construct is analyzed: a pair of semi-isolated M2 lines, connected to dense M1 wiring with a staggered V1 configuration. This design is virtually fabricated in a 10nm-like BEOL technology, complete with Trench-First SADP (self-aligned double patterning) Mx patterning, LELE (litho-etch-litho-etch double patterning) Vx patterning and advanced metallization. By varying lithography, deposition and etch processes, it is possible to see where this design construct is subject to yield-limiting mechanisms. The demo only used a small portion of the cloud. There were lots of other demos too, all of which needed their share, but the demo was able to run 89 virtual design of experiments wafers through the full process flow and a suite of 3D-DTC rules in just over an hour. If the whole cloud had been made available it would have taken just 11 minutes. It provided some tremendously valuable information about the Design-Technology sensitivities of this structure, such as the points of Minimum Insulator failure (a key reliability metric) and Minimum Metallization failures (a key resistance and reliability metric)… despite being 2D DRC clean!

But the real comparison is to the old way of doing things. That would have required the fabrication of about 200 wafers, at a cost measured in millions dollars, and a delay measured in month. I’ll take the 11 minute option.


Comments

There are no comments yet.

You must register or log in to view/post comments.