Understanding Sheath Behavior Key to Plasma Etch

Understanding Sheath Behavior Key to Plasma Etch
by Scott Kruger on 08-11-2022 at 10:00 am

Final Edit EtchingProcess Illustration

Readers of SemiWiki will be well aware of the challenges the industry has faced in photolithography in moving to new nodes, which drove the development of new EUV light sources as well as new masking techniques.  Plasma etching is another key step in chip manufacturing that has also seen new challenges in the development of new sub-10nm… Read More


SISPAD – Cost Simulations to Enable PPAC Aware Technology Development

SISPAD – Cost Simulations to Enable PPAC Aware Technology Development
by Scotten Jones on 10-31-2021 at 10:00 am

Slide11

I was invited to give a plenary address at the SISPAD conference in September 2021. For anyone not familiar with SISPAD it is a premiere TCAD conference. This year for the first time SISPAD wanted to address cost and my talk was “Cost Simulations to Enable PPAC Aware Technology Development”.

For many years the standard in technology… Read More


Webinar on coping with the complexities of 3D NAND design

Webinar on coping with the complexities of 3D NAND design
by Tom Simon on 12-03-2019 at 10:00 am

In order to beat Moore’s Law NAND Flash memories have moved from a planar topology to 3D construction. This allows for increased memory sized in much the same way a multistory building provides more building square footage on the same size building lot. Just like in building construction, adding a third dimension to the mix increases… Read More


Webinar – 3D NAND Memory Cell Optimization

Webinar – 3D NAND Memory Cell Optimization
by Tom Simon on 11-07-2019 at 10:00 am

Flash memory has become ubiquitous, so much so that it is easy to forget what life before it was like. Large scale non-volatile storage was limited spinning disks, which were bulky, power hungry and unreliable. With NAND Flash, we have become used to carrying many gigabytes around with us all the time in the form of cell phones, USB… Read More


Silvaco Talks Atoms to Systems – Where to Next?

Silvaco Talks Atoms to Systems – Where to Next?
by Randy Smith on 07-17-2019 at 10:00 am

At the ES Design West event in San Francisco last week Silvaco’s CTO and EVP of Products, Babak Taheri, gave a presentation titled, “Next Generation SoC Design: From Atoms to Systems”. The time slot for the talk was only 30-minutes which is simply not enough to discuss all the technology Silvaco is providing now. I had not looked closely… Read More


Where Circuit Simulation Model Files Come From

Where Circuit Simulation Model Files Come From
by Daniel Payne on 02-07-2019 at 7:00 am

I started out my engineering career by doing transistor-level circuit design and we used a proprietary SPICE circuit simulator. One thing that I quickly realized was that the accuracy of my circuit simulations depended entirely on the model files and parasitics. Here we are 40 years later and the accuracy of SPICE circuit simulations… Read More


Advanced Materials and New Architectures for AI Applications

Advanced Materials and New Architectures for AI Applications
by Tom Dillinger on 10-17-2018 at 7:00 am

Over the past 50 years in our industry, there have been three invariant principles:

  • Moore’s Law drives the pace of Si technology scaling
  • system memory utilizes MOS devices (for SRAM and DRAM)
  • computation relies upon the “von Neumann” architecture
Read More

Using a TCAD Tool to simulate Electrochemistry

Using a TCAD Tool to simulate Electrochemistry
by Daniel Payne on 11-02-2017 at 12:00 pm

In college I took courses in physics, calculus, chemistry and electronics on my way to earn a BSEE degree, then did an 8 year stint as a circuit designer, working at the transistor level and interacting with fab and test engineers. My next adventure was working at EDA companies in a variety of roles. As a circuit designer I knew that … Read More


Webinar on Electrochemistry and how it affects Semiconductor devices

Webinar on Electrochemistry and how it affects Semiconductor devices
by Daniel Payne on 10-09-2017 at 12:00 pm

My educational background is Electrical Engineering and I’ve learned a lot since starting in the industry back in 1978 while working on bipolar, NMOS and CMOS technology, designing DRAM, data controller and GPU devices. I continue to learn about the semiconductor industry through daily reading and attending trade shows… Read More