On Tuesday evening December 8[SUP]th[/SUP] at IEDM, Coventor held a panel discussion entitled the “The last half nanometer”. Coventor is a leading provider of simulation software used to design processes. This is my third year attending the Coventor panel discussion at IEDM and they are always excellent with very strong panels and discussion.
The panel was made up of David Fried CTO of Coventor, Alek Chen from ASML, Aaron Theon of IMEC, and Subramanian Iyer from UCLA. Subramanian acted as both a panelist and the moderator.
David Fried – CTO Coventor
David started the discussion off:
- Historically each new node saw a 15% increase in wafer cost that yielded 2x the number of die. Once yield reached around 58% of the previous generation’s yield, die cost would be the same as the previous generation.
- Recently each node is seeing a 30% increase in wafer cost yielding 1.8x the number of die. You now need to reach a yield that is 72% of the previous generation’s yield to reach the same cost per die.
- If we get to a 50% increase in wafer cost per generation for 1.5x the number of die you will need to reach 100% of the yield of the previous generation to break even on die cost and cost reductions are over.
Using multi patterning is driving a lot of 1D layout restrictions. You are getting base scaling but it isn’t enough and you are adding a lot of cost. We need EUV so we can get back to 2D layouts. A 2D layout versus a 1D layout is worth about a node of scaling.
What is after EUV, Multi-eBeam (MEB), Directed Self-Assembly (DSA)? Self-aligned isn’t new but we need it without adding structures and levels. Novels devices can enable 2D scaling, 3D XPoint is an example of nearly ideal scaling because it’s just bitlines in one direction and wordlines in the other, and additional layers invoke 3D scaling benefits.
Design restrictions hurt 2D scaling with embedded memories being particularly sensitive. You can potentially implement special design constraints that improve scaling.
Adjacent cells are an issue for memory scaling. 3D NAND is brilliant because by going vertical, they were able to make the cell bigger while still scaling the effective die area per cell. What is the equivalent approach for logic?
Tighter variation is better even if the mean is lower! This is under appreciated, variation forces more conservative designs wasting area. We also need power scaling, FinFET is the device god designed but he designed the channel and not the contacts. Contact resistance is a big issue as the device shrinks.
How do we get around all of these issues? Intelligent design, scale what you have to but back-off of other things. Is there a major design style change that can help? We need to get back to being able to do 2D designs for all layers to get the full benefits of scaling. The current requirement for multi-patterning is driving a lot of 1D layouts limiting the benefits.
Alek Chen – ASML
Control of variability is the key to shrinks. Lithography can print gratings; it is when you have to cut the gratings that problems arise.
You can use metrology and feedback to control a programmable illuminator on an exposure tool. This allows you to deal with fingerprints of previous processes. A lot of overlay issues are due to previous steps. If the alignment mark and product behavior don’t match you have a big problem.
Designers would rather have 2D at a previous node than 1D at the current node. Local interconnect is now used to provide 2D and compensate for 1D interconnect layers.
Eliminating multi-patterning reduces complexity and shortens cycle time. EUV can provide 2D layouts and simpler process flows.
Once again the same message as what David Fried noted, getting away from multi-patterning and back to 2D layouts at all layers is required to deliver the full benefit of scaling. EUV has the potential to deliver 2D layouts but it is needed now.
Aaron Theon – IMEC
1nm is one half the atomic distance of silicon.
Lines/spaces aren’t the issues, edge placement if the issue. Logic requires multiple cut masks and overlay of 1nm is ~5% error for N5. At N7 1nm = 5% change in RC max and 2% max delay energy change.
Gate and contact are competing for space.
- 1nm ~25% of a spacer
- 1nm ~ 7-8% of gate length plus contact
- 1nm ~ 20% of fin CD. In the future 1nm is ~30% of fin CD over a 1:30 to 1:50 aspect ratio.
- 1nm is 20% to 50% of HKMG
Evolve from FinFETs to stacked nanowires by releasing nanowires created within the fin using an epitaxial super-lattice. In theory the super-lattice can be controlled to within 1nm.
Selective everything is the future. Build the device from the inside out, DSA and selective Epi. Grow a super-lattice from the inside out atom by atom. You also need atomic layer etching. 0.7nm 3 sigma can be done by etch today. Deposition and etch have the potential to be more precise than lithography so design devices that are defined by deposition and etch instead of lithography.
Variation throws away nanometers of scaling.
The key is cost per function, the question now is, are we going in the right direction. The last nanometer is critical in extracting the performance from the device.
There were a couple of overall themes that all three panel members discussed:
The current practice of using multi-patterning to enable lithographic scaling is driving 1D patterns and limiting the benefits of scaling. Getting back to 2D patterns is worth a node of scaling just by itself. EUV can potentially get us back to 2D patterns while simplifying process flows and avoiding multi-patterning edge placement issues.
Variation drives more conservative design wasting area, reducing variation is another key to getting the benefits of scaling.
Novel devices structures are needed for logic similar to the 3D NAND approach where the devices critical dimensions can be controlled by deposition and etch and the cell sizes can be increased while providing die area scaling.Share this post via: