Analog Mixed-Signal Layout in a FinFET World

Analog Mixed-Signal Layout in a FinFET World
by Tom Dillinger on 03-20-2016 at 12:00 pm

The intricacies of analog IP circuit design have always required special consideration during physical layout. The need for optimum device and/or cell matching on critical circuit topologies necessitates unique layout styles. The complex lithographic design rules of current FinFET process nodes impose additional restrictions… Read More


Coventor ASML IMEC: The last half nanometer

Coventor ASML IMEC: The last half nanometer
by Scotten Jones on 01-19-2016 at 4:00 pm

On Tuesday evening December 8[SUP]th[/SUP] at IEDM, Coventor held a panel discussion entitled the “The last half nanometer”. Coventor is a leading provider of simulation software used to design processes. This is my third year attending the Coventor panel discussion at IEDM and they are always excellent with very strong panels… Read More


Moore’s Law is dead, long live Moore’s Law – part 2

Moore’s Law is dead, long live Moore’s Law – part 2
by Scotten Jones on 04-19-2015 at 12:00 am

In the first installment of this series on Moore’s law we examined what Moore’s law is and presented some data on how it has affected the industry. In this installment we will discuss the manufacturing cost reduction strategies that have made Moore’s law possible.

Manufacturing Cost Drivers
The manufacturing cost of a semiconductor… Read More