Saving Time in Physical Verification by Reusing Metadata

Saving Time in Physical Verification by Reusing Metadata
by Daniel Payne on 01-08-2020 at 10:00 am

voltage propagation cross reference data min

Physical verification is an important and necessary step in the process to tapeout an IC design, and the foundries define sign-off qualification steps for:

  • Physical validation
  • Circuit validation
  • Reliability verification

This sounds quite reasonable until you actually go through the steps only to discover that some of the … Read More


Noise, The Need for Speed, and Machine Learning

Noise, The Need for Speed, and Machine Learning
by Riko Radojcic on 05-08-2017 at 7:00 am

Technology trends make the concerns with electronic noise a primary constraint that impacts many mainstream products, driving the need for “Design-for-Noise” practices. That is, scaling, and the associated reduction in the device operating voltage and current, in effect magnifies the relative importance of non-scalableRead More


SPIE 2017 ASML and Cadence EUV impact on place and route

SPIE 2017 ASML and Cadence EUV impact on place and route
by Scotten Jones on 04-13-2017 at 7:00 am

As feature sizes have shrunk, the semiconductor industry has moved from simple, single-exposure lithography solutions to increasingly complex resolution-enhancement techniques and multi-patterning. Where the design on a mask once matched the image that would be produced on the wafer, today the mask and resulting image … Read More


Resolution Enhancement Technology – the key to Moore’s Law

Resolution Enhancement Technology – the key to Moore’s Law
by Tom Dillinger on 09-06-2015 at 10:00 am

The ability to extend photolithography utilizing 193i light sources to current process nodes is truly the key technical achievement that has enabled Moore’s Law to continue. The interplay between the exposure equipment, the materials – especially, resists and related coatings – and the fundamental principles… Read More


PDK Generation Needs Paradigm Shift

PDK Generation Needs Paradigm Shift
by Pawan Fangaria on 04-28-2015 at 4:00 pm

For any semiconductor technology node to be adopted in actual semiconductor designs, the very first step is to have a Process Design Kit (PDK) developed for that particular technology node and qualified through several design tools used in the design flow. The development of PDK has not been easy; it’s a tedious, time consuming,… Read More


The Matrix, your ultimate OPC

The Matrix, your ultimate OPC
by Beth Martin on 05-06-2014 at 12:47 pm

One of the many consequences of shrinking process nodes is that traditional OPC can no longer achieve good pattern fidelity with reasonable turn-around-time. But there is a solution; we made it ourselves and call it matrix OPC.

First, let’s explore the problems with traditional optical proximity correction (OPC) when applied… Read More


One SPIE session not to miss

One SPIE session not to miss
by Beth Martin on 02-19-2014 at 4:19 pm

The time is nigh for another meeting of the practitioners of the lithographic arts, dark and otherwise, at the SPIE Advanced Lithography symposium.

I love this conference for the engagement you see, both in the sessions and in the hallways. People actually meet and talk and argue. There’s always interesting gossip, exciting technologies,… Read More


Cutting the Key to 14nm Lithography

Cutting the Key to 14nm Lithography
by Beth Martin on 04-08-2013 at 2:30 pm

It appears that immersion lithography is now the plan of record for manufacturing ICs at 14nm. How is it possible to use 193nm wavelength light at 14nm? How can we provide the process window to pattern the such tight pitches? The secret lies in computational lithography. For 20nm, the two key innovations in computational lithography… Read More


Magic? No! It’s Computational Lithography

Magic? No! It’s Computational Lithography
by Beth Martin on 02-11-2013 at 7:00 am

The industry plans to use 193nm light at the 20nm, 14nm, and 10nm nodes. Amazing, no? There is no magic wand; scientists have been hard at work developing computational lithography techniques that can pull one more rabbit out of the optical lithography hat.

Tortured metaphors aside, the goal for the post-tapeout flow is the same… Read More


GLOBALFOUNDRIES and Mentor Develop Methods to Identify Critical Features in IC Designs

GLOBALFOUNDRIES and Mentor Develop Methods to Identify Critical Features in IC Designs
by glforte on 11-28-2012 at 3:00 pm

Since the beginning of the semiconductor industry, improving the rate of yield learning has been a critical factor in the success silicon manufacturing. Each fab has dedicated yield teams that look at the yield of wafers manufactured the previous day and attempt to find the root cause of any unexpected “excursions.” In earlier… Read More