WP_Term Object
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 423
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 423
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
    [is_post] => 1

SPIE 2017 ASML and Cadence EUV impact on place and route

SPIE 2017 ASML and Cadence EUV impact on place and route
by Scotten Jones on 04-13-2017 at 7:00 am

As feature sizes have shrunk, the semiconductor industry has moved from simple, single-exposure lithography solutions to increasingly complex resolution-enhancement techniques and multi-patterning. Where the design on a mask once matched the image that would be produced on the wafer, today the mask and resulting image often look completely different. In addition, the advent of multi-patterning has led to patterns being broken up into multiple colors, with each “color” being produced by a different mask and a single layer on a wafer requiring two to five masks to produce. Designs must be carefully optimized to ensure that the resulting wafer images are free of “hotspots” that can lead to low yields.

At the SPIE Advanced Lithography Conference Cadence, ASML and imec presented “In-design and signoff lithography physical analysis for 7/5nm” and Cadence and ASML announced a partnership and new joint product to address lithography optimization. I saw the paper presented and had a chance to sit down with Cadence and ASML and discuss the paper and their partnership.

At 65nm there were <1,000 design rules a design had to meet, at 10nm close to 6,000 design rules are required and the design rules are more complex, see figure 1. Also at 45nm the optical range of influence was part of one standard cell and if the cell was good you could then put the cells right next to each other in your design. For current processes the range of optical influence is up to 10 standard cells and you have to evaluate multiple cells to insure good yield!

Figure 1. Design rule count versus node.

Cadence is a leading producer of design solutions for the semiconductor industry with a broad position in EDA as well as a leader in analog and digital design and IP. Cadence’s new Litho Physical Analyzer – Production Lithography Unified Solution (PLUS) tool analyzes the interactions between designs and lithography to improve yields, meet foundry design for manufacturability (DFM) requirements and integrates with Cadence layout tools.

ASML is the leading provider of lithography exposure tools today and they have built a large market share doing optical proximity correction for foundries and IDMs.

The partnership between Cadence and ASML allows the design to be coupled to OPC and lithography. ASML provides actual production lithography models to integrate into the Cadence LPA tool creating an integrated solution called LPA PLUS. With LPA PLUS the impact of lithography on power and timing can now be evaluated and optimized. You can correct for hot spots right in the place and route tool and see the impact on power and timing. In the past, a designer would send a design to a foundry and expect their design intent to be met but the foundry might have to fix a hot spot for yield issues and in the process, impact the power and timing of the design.

AMD is a leader in the application of design for manufacturing and has been quick to recognize the partnership-enabled added value of LPA PLUS in meeting their requirements.

In the paper that was presented imec used the LPA PLUS tool to compare a single EUV exposure to an SAQP process with an EUV cut mask for metal 1 (42nm pitch) and metal 2 (32nm pitch) for the imec N7 node. The LPA PLUS tool enabled them to do a Design Technology Co Optimization (DTCO). While both EUV single exposure and SAQP + EUV cut are viable approaches, it was found using the LPA PLUS tool that the SAQP + EUV cut approach resulted in longer average wire lengths with higher parasitic capacitance (~9%) significantly increasing power consumption (~4%), see figure 2.

Figure 2. EUV impact on place and route.

The LPA PLUS tool meets the run time goals of the partnership to evaluate a small block over a coffee break (15 minutes), a sector over lunch (70 minutes) and a complete core overnight (720 minutes). By optimizing each block as it is being designed you only have a few issues to work through when you get to the full chip level.

The partnership between Cadence and ASML makes a lot of sense in terms of addressing the customer needs. ASML was hearing they needed to be more layout-aware and Cadence needed to improve the lithography modeling. The two companies make good partners because they are both strong in their respective areas with little overlap.

The Cadence-ASML partnership to deliver the LPA PLUS provides the integrated design-lithography environment required for today’s leading edge designs.

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