Electronics Design for Manufacturability (DfM): Avoiding Failure After Reflow

Electronics Design for Manufacturability (DfM): Avoiding Failure After Reflow
by Admin on 06-18-2020 at 11:00 am

June 18, 2020

11:00 AM (EDT)

Venue:
Online

In the electronics industry, the capability of manufacturing suppliers greatly impacts the quality and reliability of any product. Manufacturing issues are one of the top reasons that companies fail to meet warranty expectations. Both process and design can play critical roles during

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Saving Time in Physical Verification by Reusing Metadata

Saving Time in Physical Verification by Reusing Metadata
by Daniel Payne on 01-08-2020 at 10:00 am

voltage propagation cross reference data min

Physical verification is an important and necessary step in the process to tapeout an IC design, and the foundries define sign-off qualification steps for:

  • Physical validation
  • Circuit validation
  • Reliability verification

This sounds quite reasonable until you actually go through the steps only to discover that some of the … Read More


Tools for Advanced Packaging Design Follow Moore’s Law, Too!

Tools for Advanced Packaging Design Follow Moore’s Law, Too!
by Tom Dillinger on 06-05-2017 at 9:00 am

There is an emerging set of advanced packaging technologies that enables unique product designs, with the capability to integrate multiple die, from potentially heterogeneous technologies. These “system-in-package” (SiP) offerings provide architects with the opportunity to optimize product performance, power, cost,… Read More


Noise, The Need for Speed, and Machine Learning

Noise, The Need for Speed, and Machine Learning
by Riko Radojcic on 05-08-2017 at 7:00 am

Technology trends make the concerns with electronic noise a primary constraint that impacts many mainstream products, driving the need for “Design-for-Noise” practices. That is, scaling, and the associated reduction in the device operating voltage and current, in effect magnifies the relative importance of non-scalableRead More


SPIE 2017 ASML and Cadence EUV impact on place and route

SPIE 2017 ASML and Cadence EUV impact on place and route
by Scotten Jones on 04-13-2017 at 7:00 am

As feature sizes have shrunk, the semiconductor industry has moved from simple, single-exposure lithography solutions to increasingly complex resolution-enhancement techniques and multi-patterning. Where the design on a mask once matched the image that would be produced on the wafer, today the mask and resulting image … Read More


Mentor’s Battle of the Photonic Bulge

Mentor’s Battle of the Photonic Bulge
by Mitch Heins on 12-07-2016 at 4:00 pm

A few weeks back I wrote an article mentioning that Mentor Graphics has been quietly working on solutions for photonic integrated circuits (PICs) for some time now, while one of their competitors has recently established a photonics beachhead. One of the most common challenges for PIC designs is their curvilinear nature, thus… Read More


Layout Pattern Matching for DRC, DFM, and Yield Improvement

Layout Pattern Matching for DRC, DFM, and Yield Improvement
by Tom Dillinger on 06-01-2016 at 12:00 pm

It is truly amazing to consider the advances in microelectronic process development, using 193i photolithography. The figure below is a stark reminder of the difference between the illuminating wavelength and the final imaged geometries. This technology evolution has been enabled by continued investment in mask data generation… Read More


Bridging Design Environments for Advanced Multi-Die Package Verification

Bridging Design Environments for Advanced Multi-Die Package Verification
by Tom Dillinger on 03-28-2016 at 12:00 pm

This year is shaping up to be an inflection point, when multi-die packaging technology will experience tremendous market growth. Advanced 2.5D/3D package offerings have been available for several years, utilizing a variety of technologies to serve as the package substrate, interposer material for embedding die micro-bump… Read More


Samsung: the Journey to 14nm and 10nm

Samsung: the Journey to 14nm and 10nm
by Paul McLellan on 06-24-2015 at 7:00 pm

At the Samsung theatre (cutely named the Samsung Open Collaboration (SoC) theater) I watched a presentation by KK Lin on using DFM to bring up their 14nm and 10nm processes. And yes, they are real. Here is a picture I took of a 14nm wafer and a 10nm wafer. Samsung announced that they would ramp 10n to volume production by the end of next… Read More


Accelerate Modern PCB Design and Manufacturing

Accelerate Modern PCB Design and Manufacturing
by Pawan Fangaria on 05-24-2015 at 12:00 pm

In modern electronic industry PCBs are required to accommodate highly dense circuits with large number of components and complex routing spaces. While the complexity is increasing, the time-to-market is decreasing. In such a scenario, there is no other option than to reduce the design time by employing innovative editing options… Read More