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Symmetry Requirements Becoming More Important and Challenging

Symmetry Requirements Becoming More Important and Challenging
by Tom Simon on 08-24-2021 at 10:00 am

Humans certainly have always had an aesthetic preference for symmetry. We also see symmetry showing up frequently in nature. The importance of symmetry in electronic designs has been apparent for decades. There are a host of analog structures that require balanced layout. For instance, these include differential pairs and current mirrors. Or sometimes sets of devices need to be matched for performance reasons. Even starting with a schematic clearly drawn to show the symmetrical relationship between elements among devices, there is no guarantee that the layout derived from it will possess similar symmetry. Siemens EDA has developed new features in their Calibre nmPlatform to help with these issues and several new symmetry issues that designers should mindful of. Sherif Hany at Siemens has written an informative white paper that covers these new features so that designers can see how symmetry verification can be added to their flows to help quickly find and fix them before tapeout.

Symmetry across the design flow
Symmetry across the design flow

Even when correct by construction techniques are used to help implement symmetry, there are a lot of factors that can degrade the design. Despite common centroid placement, routing to devices can end up mismatched. Likewise, other factors such as dummy shielding devices, metal fill and DFM processing can adversely affect layout symmetry. Siemens has developed techniques that are context aware from a schematic perspective to ensure that symmetry is properly adhered to. Double patterning is another area where symmetry in a design can suffer. Calibre nmPlatform can help resolve this with symmetry-assisted color anchoring. The white paper offers an illustration of how this works.

When metal fill is added to meet chemical-mechanical-polishing requirements design symmetry can also be affected. Thus, both the original design and the filled design must be verified. It is now possible for some fill decks to incorporate symmetry checks to guide fill operations around sensitive metals.

The paper discusses the advantages even where designs are not at advanced nodes or designers may already have in-house developed checks in place. Sherif suggests that in house checks usually come with a fair amount of designer effort and are not necessarily comprehensive. Even though foundry rule decks do preliminary symmetry checks, extra checks can offer significant benefits. Siemens has implemented advanced checks that go far beyond the foundry supplied rule decks. These advanced checks can be extremely helpful in automotive applications, MEMS, silicon photonics or analog/RF.

Another concern that Sherif addresses in the white paper is how some verification solutuions are overly strict and report so many errors that the results are not useful. Apparently, there is such a thing as too accurate. Calibre implements a fuzzy symmetry capability that allows for tolerances by area or length to help make the results more useful. This can be especially useful for curvilinear structures that can have minor variations that are not significant.

There is also a discussion of the debugging features for the symmetry analysis. XOR results can be shown in the layout environment, which makes for easy debugging. Also results can be seen in Calibre RealTime tools. There is integration with Calibre PERC, using XML. Customization of the symmetry checks can easily be set up and modified to suit individual project needs.

The paper closes by asserting that, like other parts of the verification flow, symmetry checks are becoming more complicated and are increasingly necessary. Without a doubt designers will want to be able to fully check for symmetry issues before tapeout. It seems that Siemens is mindful of this and has taken a comprehensive approach to solving this challenge for designers. More information and the full white paper are available on the Siemens website.

Also Read:

Debugging Embedded Software on Veloce

SoC Vulnerabilities

A Custom Layout Environment for SOC Design Closure

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